Toshiba H1 Series - Manual (Page 451)

TMP92CZ26A
92CZ26A-448
3.16.8 USB Device answer
USB controller (UDC) sets various register and initialization in UDC in detecting of
hardware reset, detecting of USB bus reset, and enumeration answer.
Below is explaining about each condition.
(1) Condition in detect in bus reset.
When UDC detects bus reset on USB signal line, it initializes internal register, and it
prepares enumeration operation from USB host. After detect in USB reset, UDC sets
ENDPOINT0 to control transfer type 8-byte payload and default address for using
default pipe. And endpoint except for it is prohibited.
Register name Initial value
ENDPOINT STATUS EP0 40H
Except for EP0 5CH
(2) Detail of STATUS register
Status register that was prepared every endpoint shows condition of every endpoint
in UDC.
Each condition affects transfer various USB. Condition changing in each transfer
type refers to chapter 5.
EPx_STATUS register value is 0 to 3, and it shows conditions of below. 0 to 4 are
result of various transfers. It can be confirmed previous result that is transferred to
endpoint by confirming from external of UDC.
0 READY
1 DATAIN
2 FULL
3 TX_ERR
4 RX_ERR
These conditions mean that endpoint operate normally. Meaning that is showed is
different every transfer mode. Therefore, please refer to below each transfer mode
column.