Toshiba H1 Series - Manual (Page 372)

TMP92CZ26A
92CZ26A-369
3.16.2 900/H1 CPU I/F
The 900/H1 CPU I/F is a bridge between 900/H1 CPU and UDC and it mainly works
following operations.
• INTUSB (interrupt from UDC) generation
• A bridge for SFR
• USB clock control (48 MHz)
3.16.2.1 SFRs
The 900/H1 CPU I/F have following SFRs to control UDC and USB transceiver.
• USB control
USBCR1 (USB control register 1)
• USB interrupt control
USBINTFR1 (USB interrupt flag register 1)
USBINTFR2 (USB interrupt flag register 2)
USBINTFR3 (USB interrupt flag register 3)
USBINTFR4 (USB interrupt flag register 4)
USBINTMR1 (USB interrupt mask register 1)
USBINTMR2 (USB interrupt mask register 2)
USBINTMR3 (USB interrupt mask register 3)
USBINTMR4 (USB interrupt mask register 4)
Figure 3.16.2 900/H1 CPU I/F SFR
Address Read/Write SFR Symbol
07F0H R/W USBINTFR1
07F1H R/W USBINTFR2
07F2H R/W USBINTFR3
07F3H R/W USBINTFR4
07F4H R/W USBINTMR1
07F5H R/W USBINTMR2
07F6H R/W USBINTMR3
07F7H R/W USBINTMR4
07F8H R/W USBCR1