7 bus interface and access to fifo – Toshiba H1 Series User Manual
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TMP92CZ26A
92CZ26A-442
3.16.7 Bus Interface and Access to FIFO
(1) CPU bus interface
UDC prepares two types of FIFO access, single packet and dual packet. In single
packet mode, FIFO capacity that is implemented by hardware is used as big FIFO. In
dual packet mode, FIFO capacity that is divided into two is used as two FIFOs. And it
uses as independent FIFO. Even if UDC is transmitting and receiving to USB host, it
can be used bus efficient by to possible load to FIFO.
But control transfer type receives only single packet mode.
Epx_SINGLE signal in dual packet mode must be fixed to “0”. If this signal is fixed to
“0”, FIFO register runs in single mode.
Sample: If you use endpoint 1 to dual packet of payload 64 bytes.
EP1_FIFO size
:
Prepare 128 bytes
EP1_SINGLE signal
:
Hold 0
EP1 Descriptor setting
Direction
:
Optional
Max payload size
:
64 bytes
Transfer
mode
:
Optional