Figure 3.23.9 ad conversion registers – Toshiba H1 Series User Manual
Page 606
TMP92CZ26A
92CZ26A-603
High-priority AD Conversion Result Register SP Low
7 6 5 4 3 2 1 0
bit
Symbol
ADRSP1
ADRSP0
OVSRP
ADRSPRF
Read/Write R
R
R
After
reset
0
0 0
0
Function
Store Lower 2 bits of an
AD conversion result
Overrun
flag
0:No generate
1: Generate
AD conversion
result store
flag
1: Stored
High-priority AD Conversion Result Register SP High
7 6 5 4 3 2 1 0
bit
Symbol ADRSP9 ADRSP8 ADRSP7
ADRSP6
ADRSP5
ADRSP4 ADRSP3 ADRSP2
Read/Write R
After
reset
0 0 0 0 0 0 0 0
Function
Store Upper 8 bits of an AD conversion result
9
8
7
6
5
4
3
2
1
0
Channel X conversion result
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Figure 3.23.9 AD Conversion Registers
ADREGSPL
(12B0H)
ADREGSPH
(12B1H)
ADREGxH ADREGxL
• Bits
5
∼ 2 are always read as “0”.
•
Bit 0 is the AD conversion result store flag <ADRxRF>. When AD conversion result is stored, the flag is set to “1”.
When Lower register (ADRECxL) is read, this bit is cleared to “0”.
•
Bit 1 is the Overrun flag <OVRx>. This bit is set to “1” if a next conversion result is written to the ADREGxH/L
before both the ADREGxH and ADREGxL are read. This bit is cleared to “0” by reading Flag.