Toshiba H1 Series User Manual

Page 363

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TMP92CZ26A

92CZ26A-360

When the <TRX> is “0” (Receiver mode)

When the next transmitted data is other than 8 bits, set <BC2:0> <ACK> and

read the received data from SBIDBR to release the SCL line (data which is read
immediately after a slave address is sent is undefined). After the data is read,
<PIN> becomes “1”.

Serial clock pulse for transferring new 1 word of data is defined SCL and

outputs “L” level from SDA pin with acknowledge timing.

An INTSBI interrupt request then occurs and the <PIN> becomes “0”, Then the

TMP92CZ26A pulls down the SCL pin to the Low-level. The TMP92CZ26A
outputs a clock pulse for 1-word of data transfer and the acknowledge signal each
time that received data is read from the SBIDBR.

Figure 3.15.16 Example of when <BC2:0>

= “000”, <ACK> = “1” in receiver mode

In order to terminate the transmission of data to a transmitter, clear <ACK> to

“0” before reading data which is 1-word before the last data to be received. The
last data word does not generate a clock pulse as the Acknowledge signal. After
the data has been transmitted and an interrupt request has been generated, set
<BC2:0> to “001” and read the data. The TMP92CZ26A generates a clock pulse
for a 1-bit data transfer. Since the master device is a receiver, the SDA line on the
bus remains High. The transmitter interprets the High signal as an ACK signal.
The receiver indicates to the transmitter that data transfer is complete.
After the one data bit has been received and an interrupt request been generated,
the TMP92CZ26A generates a stop condition (see Section 3.15.6 (4) Stop
condition generation) an
d terminates data transfer.

Figure 3.15.17 Termination of data transfer in master receiver mode

SCL pin

D7

Acknowledge signal
to a transmitter

1

SDA pin

2

3

4

5

6

7

8

9

D6 D5 D4

D3

D2

D1

<PIN>

INTSBI

interrupt request

ACK

Output from Master
Output from Slave

D0

Read SBIDBR

New D7

SCL pin

D7

Acknowledge signal
sent to a transmitter

1

SDA pin

2

3

4

5

6

7

8

1

D6 D5

D4

D3

D2

D1

<PIN>

INTSBI

interrupt request

Output of Master
Output of Slave

D0

“0”

→ <ACK>

Read SBIDBR

“001”

→ <BC2:0>

Read SBIDBR

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