Event status bit definitions, Status byte bit definitions – Quantum Data 801GC User Manual

Page 194

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6-68

Chapter 6: Programming

Model 801GC, 801GF & 801GX¥Rev. A

Event Status Bit Definitions

OPC

Operation complete. Indicates that all
operations have been completed.

RQC

Request control. Indicates that a device is
requesting control. The 801GX will never
request control, so this bit will always be 0.

QYE

Query error. Indicates that a query request
was made while the 801GX was in deadlock.

DDE

Device dependent error. Indicates that the
801GX encountered an error executing a
command.

EXE

Execution error. Indicates that there was an
error parsing a parameter.

CME

Command error. Indicates that there was an
unrecognizable command.

URQ

User request. Indicates that a front panel
button has been pressed or that the front
panel knob has been turned.

PON

Power on. Indicates that power has been
turned off-and-on. This bit will always be 0
in the 801GX.

Status Byte Bit Definitions

MAV

Message available. Indicates that at least one
complete response is present in the output
buffer.

ESB

Event status bit. Indicates that one of the
enabled conditions in the Standard Event
Status register is set.

MSS

Master summary status. Indicates that the
801GX has a reason for requesting service.

RQS

Request service. This bit is read only by
executing a serial poll of the 801GX.

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