AMD SB600 User Manual

Page 109

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©2008 Advanced Micro Devices, Inc.

SMBus Module and ACPI Block (Device 20, Function 0)

AMD SB600 Register Reference Manual

Proprietary

Page 109

UsbEnable - RW - 8 bits - [PCI_Reg: 68h]

Field Name

Bits

Default

Description

OHCI_2_enable

3

1b

Set to 1 to enable OHCI_2

OHCI_3_enable

4

1b

Set to 1 to enable OHCI_3

OHCI_4_enable

5

1b

Set to 1 to enable OHCI_4

Reserved 7:6

00b

UsbEnable register

SeriallrqControl- RW - 8 bits - [PCI_Reg: 69h]

Field Name

Bits

Default

Description

NumStartBits

1:0

00b

This field defines the number of clocks in the start frame.
Start Frame Width = 4 + 2 * NumStartBits

NumSerIrqBits

5:2

0h

Total number of serial IRQ's = 17 + NumSerIrqbits
0 - 17 serial IRQ's (15 IRQ, SMI#, + IOCHK#)
1 - 18 serial IRQ's (15 IRQ, SMI#, IOCHK#, INTA#)
...
15 - 32 serial IRQ's
The SB600 serial IRQ can support 15 IRQ#, SMI#, IOCHK#,
INTA#, INTB#, INTC#, and INTD#.
When serial SMI# is used, BIOS will need to check SIO (or
device that generates serial SMI#) for status.

SerIrqMode

6

0b

0 - Continuous mode
1 - Active (quiet) mode

SerialIrqEnable

7

0b

Setting this bit to 1 enable the serial IRQ function

SeriallrqControl register

RTCProtect- RW - 8 bits - [PCI_Reg: 6Ah]

Field Name

Bits

Default

Description

RTCProtect38_3F

0

0b

When set, RTC RAM index 38:3Fh will be locked from
read/write. This bit can only be written once.

RTCProtectF0_FF

1

0b

When set, RTC RAM index F0:FFh will be locked from
read/write. This bit can only be written once.

RTCProtectE0_EF

2

0b

When set, RTC RAM index E0:EFh will be locked from
read/write. This bit can only be written once.

RTCProtectD0_DF

3

0b

When set, RTC RAM index D0:DFh will be locked from
read/write. This bit can only be written once.

RTCProtectC0_CF

4

0b

When set, RTC RAM index C0:CFh will be locked from
read/write. This bit can only be written once.

Reserved 7:5

000b

RTCProtect register

USB Reset- RW - 8 bits - [PCI_Reg: 6Bh]

Field Name

Bits

Default

Description

Force Reset to USB Host
Controllers

4:0

00h

These are software control bits that force the reset of the USB
host controllers.

Force USB Port PHY
Power Down

5

0b

Forces USB PHY into power down mode.

Force PHY PLL Power
Down

6

0b

Forces USB PHY PLL into power down mode.

Force USB Port PHY
Reset

7

0b

Forces USB PHY reset.

USB Reset register

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