AMD SB600 - Manual (Page 75)

©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual Proprietary Page 75
EHCI Misc Control – RW - 32 bits - [PCI_Reg : 50h]
Field Name Bits Default Description
Disable Async QH Cache
on OUT xfer 25 0b Set to 1 to disable async QH/QTD cache during OUT xfer.
Disable Async Data
Cache 26 0b Set to 1 to disable async data cache request.
Disable Periodic List
Cache 27 0b Set to 1 to disable periodic list cache.
Reserved 31:28 0h Reserved
SBRN – R - 8 bits - [PCI_Reg : 60h]
Field Name Bits Default Description
SBRN 7:0 20h Hard-wired to 20h.
FLADJ – RW - 8 bits - [PCI_Reg : 61h]
Field Name Bits Default Description
FLADJ 5:0 20h Frame Length Timing Value. Each decimal value change to
this register corresponds to 16 high-speed
bit times. The SOF cycle time (number of SOF counter clock
periods to generate a SOF micro-frame length) is equal to
59488 + value in this field. The default value is decimal 32
(20h), which gives a SOF cycle time of 60000.
FLADJ Value in decimals
[hexadecimal value]
Frame Length
(# High Speed bit
times in decimals)
0 [00h] 59488
1 [01h] 59504
2 [02h] 59520
… …
31 [1Fh] 59984
32 [20h] 60000
… …
62 [3Eh] 60480
63 [3Fh] 60496
Reserved 7:6 Reserved.
PME Control – RW - 32 bits - [PCI_Reg : C0h]
Field Name Bits Default Description
Cap_ID 7:0 01h Read only.
A value of “01h” identifies the linked list item as being the
PCI Power Management registers.
Next ItemPointer 15:8 D0h Read only.
This field provides an offset into the function’s PCI
Configuration Space pointing to the location of next item in
the function’s capability list. If there are no additional items
in the Capabilities List, this register is set to 00h.
Version 18:16 010b Read only.
A value of “010b” indicates that this function complies with
Revision 1.1 of the PCI Power Management Interface
Specification.
PME clock 19 0b Read only.
When this bit is a “0”, it indicates that no PCI clock is
required for the function to generate PME#.
Reserved 20 Reserved