AMD SB600 - Manual (Page 94)

©2008 Advanced Micro Devices, Inc. OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual Proprietary Page 94
Control / Status – RW - 32 bits - [DBUG_Reg : DBase + 00h]
Field Name Bits Default Description
Enabled 28 0b This bit is a one if the debug port is enabled for operation.
Software can clear this by writing a zero to it. The controller clears the
bit for the same conditions where hardware clears the Port
Enable/Disable Change bit (in the PORTSC register). (Note: this bit is
not cleared when System Software clears the Port Enabled/Disabled bit
(in the PORTSC register). Software can directly set this bit, if the port is
already enabled in the associated Port Status and Control register (this
is HW enforced).
Reserved 29 Reserved
Owner 30 0b When debug software writes a one to this bit, the ownership of the
debug port is forced to the EHCI controller (i.e. Immediately taken away
from the companion controller). If the port was already owned by the
EHCI controller, then setting this bit is has no effect. This bit overrides
all of the ownership related bits in the standard EHCI registers. Reset
default = 0. Note that the value in this bit may not affect the value
reported in the Port Owner bit in the associated PORTSC register.
Reserved 31 Reserved
USB PIDs – RW - 32 bits - [DBUG_Reg : DBase + 04h]
Field Name Bits Default Description
Token PID 7:0 00h The debug port controller sends this PID as the Token PID for each
USB transaction. Software will typically set this field to either IN, OUT
or SETUP PID values. Reset default = undefined.
Send PID 15:8 00h The debug port controller sends this PID to begin the data packet when
sending data to USB (i.e. Write/Read# is asserted). Software will
typically set this field to either DATA0 or DATA1 PID values. Reset
default = undefined.
Received PID 23:16 00h Read Only
The debug port controller updates this field with the received PID for
transactions in either direction. When the controller is sending data
(Write/Read# is asserted), this field is updated with the handshake PID
that is received from the device. When the host controller is receiving
data (Write/Read# is not asserted), this field is updated with the data
packet PID (if the device sent data), or the handshake PID (if the device
NAKs the request). This field is valid when the controller sets the Done
bit. Reset default = undefined.
Reserved 31:24 Reserved