AMD SB600 User Manual

Page 294

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©2008 Advanced Micro Devices, Inc.

Real Time Clock (RTC)

AMD SB600 Register Reference Manual

Proprietary

Page 294

Register C - R – 8 bits - [RTC_Reg: 0Ch]

Field Name

Bits

Default

Description

Update Ended Interrupt Flag(UF)

4

0b

This bit is set to one after each update cycle.
Reading Register C clears UF.

Alarm Interrupt Flag (AF)

5

0b

This bit is set to one if second, minute and hour time
has matched the second, minute and hour alarm
time. Reading Register C clears AF bit.

Periodic Interrupt Flag (PF)

6

0b

This bit is set to one when an edge is detected on
the selected tap (through RS3 to RS0) of the
frequency divider. Reading Register C clears PF bit.

Interrupt Request Flag (IRQF)

7

0b

Logically, IRQF =
(PF*PIE)+(AF*AIE)+(UF*UIE)+(WF*WIE) where WF
and WIE are defined in Extended Control Register
4A and 4B. Reading Register C clears IRQF bit.
Any time the IRQF bit is set to one, the #IRQ pin is
driven low.

Register C: Control register

DateAlarm - RW – 8 bits - [RTC_Reg: 0Dh]

Field Name

Bits

Default

Description

DateAlarm

5:0

00h

DateAlarm in BCD format and is considered when it is
set to non-zero value. If this value is set to 0, then date
is not compared for alarm generation.

Scratchbit 6

0b

VRT

7

1b

Valid RAM and Time; refer to VRT_T1 and VRT_T2
registers (PMIO 3E/3F)

Date Alarm Register

AltCentury - RW – 8 bits - [RTC_Reg: 32h]

Field Name

Bits

Default

Description

AltCentury

7:0

00h

(This register is accessed only when DV0=0 and
PM_Reg 7Ch Bit4=1.) Binary-Code-Decimal format.
Leap year correction is done through hardware. This
register can be set by software (SET bit of Register B =
1) or can be automatically updated by hardware every
century. When set by software, hardware updating is
disabled.

AltCentury Register

Century - RW – 8 bits - [RTC_Reg: 48h]

Field Name

Bits

Default

Description

Century

7:0

00h

(This register is accessed only when DV0=1) Binary-
Code-Decimal format. Leap year correction is done
through hardware. This register can be set by software
(SET bit of Register B = 1) or can be automatically
updated by hardware every century. When set by
software, hardware updating is disabled.

Century Register

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