AMD SB600 User Manual
Page 20
©2008 Advanced Micro Devices, Inc.
SATA Registers (Device 18, Function 0)
AMD SB600 Register Reference Manual
Proprietary
Page 20
PCI Power Management Control And Status - RW- 16 bits - [PCI_Reg:64h]
Field Name
Bits
Default
Description
Power State
1:0
00b
This field is used both to determine the current power state
of the HBA and to set a new power state. The values are:
00 – D0 state
11 – D3
HOT
state
The D1 and D2 states are not supported. When in the
D3
HOT
state, the configuration space is available, but the
register memory spaces are not. Additionally, interrupts
are blocked.
Reserved 7:2
Reserved
PME Enable
8
0b
Read-only. Hard-wired to ‘0’ indicates PME disable
Reserved 14:9
Reserved.
PME Status
15
0b
Read-only. Hard-wired to ‘0’ as PME disable
Serial ATA Capability Register 0 - R- 32 bits - [PCI_Reg:70h]
Field Name
Bits
Default
Description
Capability ID
7:0
12h
Capability ID. Indicates this is a Serial ATA Capability ID.
Capability Next Pointer
15:8
00h
Next Pointer, end of the list.
Minor Revision
19:16
0h
Minor revision number of the SATA Capability Pointer
implemented.
Major Revision
23:20
1h
Major revision number of the SATA Capability Pointer
implemented.
Reserved 31:24
Reserved
Serial ATA Capability Register 1 - R- 32 bits - [PCI_Reg:74h]
Field Name
Bits
Default
Description
BAR Location
3:0
1111b
Value 1111b indicates that the Index-Data Pair is implemented
in Dwords directly following SATACR1 in the PCI configuration
space.
BAR Offset
23:4
00000h
Indicates the offset into the BAR where the Index-Data Pair
are located in Dword granularity. Since the BAR location is
setting at 1111b, this field is not used anymore.
Reserved 31:24
Reserved
IDP Index Register - RW- 32 bits - [PCI_Reg:78h]
Field Name
Bits
Default
Description
Reserved 1:0
Reserved
IDP Index
9:2
00h
This register selects the Dword offset of the memory mapped
AHCI register to be accessed. The IDP Index should be sized
such that it can access the entire ABAR register space for the
particular implementation. See Note.
Reserved 31:10
Reserved
Note: ABAR is AHCI memory map registers located at AHCI base address (BAR5) space.
IDP Data Register - RW- 32 bits - [PCI_Reg:7Ch]
Field Name
Bits
Default
Description
IDP Data
31:0
This register is a “window” through which data is read or
written to the memory mapped register pointed to by the IDP
Index register. Note that a physical register is not actually
implemented as the data is actually stored in the memory
mapped registers.
Since this is not a physical register, the “default” value is the
same as the default value of the register pointed to by IDP
Index.
All register accesses to IDP Data are Dword granularity