AMD SB600 User Manual
Page 159
©2008 Advanced Micro Devices, Inc.
SMBus Module and ACPI Block (Device 20, Function 0)
AMD SB600 Register Reference Manual
Proprietary
Page 159
SmiSciSts2 - RW – 8 bits - [PM_Reg: 5Ch]
Field Name
Bits
Default
Description
ExtEvent0Status
0
0b
This bit indicates the SMI# status of ExtEvent0 to
SCI/Wakeup if it is configured to generate SMI# followed by
SCI
ExtEvent1Status
1
0b
This bit indicates the SMI# status of ExtEvent1 to
SCI/Wakeup if it is configured to generate SMI# followed by
SCI
PCIePmeStatus
2
0b
This bit indicates the SMI# status of the PME# from
PCIExpress if it is configured to generate SMI# followed by
SCI
GPM0Status
3
0b
This bit indicates the SMI# status of GPM[0] to SCI/Wakeup if
it is configured to generate SMI# followed by SCI
GPM1Status
4
0b
This bit indicates the SMI# status of GPM[1] to SCI/Wakeup if
it is configured to generate SMI# followed by SCI
GPM2Status
5
0b
This bit indicates the SMI# status of GPM[2] to SCI/Wakeup if
it is configured to generate SMI# followed by SCI
GPM3Status
6
0b
This bit indicates the SMI# status of GPM[3] to SCI/Wakeup if
it is configured to generate SMI# followed by SCI
GPM8Status
7
0b
This bit indicates the SMI# status of GPM[8] to SCI/Wakeup if
it is configured to generate SMI# followed by SCI
SmiSciSts2 register
SmiSciSts3 - RW – 8 bits - [PM_Reg: 5Dh]
Field Name
Bits
Default
Description
Gpio0Status
0
0b
This bit indicates the SMI# status of GPIO0 (or
WAKE#/GEVENT8 pin if PM IO Reg 84h bit1 =1) to
SCI/wakeup if it is configured to generate SMI# followed by
SCI
GPM4Status
1
0b
This bit indicates the SMI# status of GPM[4] to SCI/Wakeup if
it is configured to generate SMI# followed by SCI
GPM5Status
2
0b
This bit indicates the SMI# status of GPM[5] to SCI/Wakeup
AzaliaStatus
3
0b
This bit indicates the SMI# status from the internal HD Audio
controller if it is configured to generate SMI# followed by SCI
GPM6Status
4
0b
This bit indicates the SMI# status of GPM[6] to SCI/Wakeup if
it is configured to generate SMI# followed by SCI
GPM7Status
5
0b
This bit indicates the SMI# status of GPM[7] to SCI/Wakeup if
it is configured to generate SMI# followed by SCI
Gpio2Status
6
0b
This bit indicates the SMI# status of GPIO2 to SCI/wakeup if
it is configured to generate SMI# followed by SCI
SataSciStatus
7
0b
This bit indicates the SMI# status of SataSci to SCI/wakeup
SmiSciSts3 register
MwaitEnable - RW – 8 bits - [PM_Reg: 5Eh]
Field Name
Bits
Default
Description
Mwait_any_smi_en
0
0b
SMI# is generated when any CPU is in mwait state if this bit
is set to 1
Mwait_2cpu_smi_en
1
0b
For 2 CPU system (dual core, non HT) SMI# is generated
when both CPUs are in mwait state if this bit is set to 1
Mwait_4cpu_smi_en
2
0b
For 4 CPU system (dual core, HT) SMI# is generated when
all 4 CPUs are in mwait state if this bit is set to 1
Mwait_2cpu_C23_en 3 0b
For 2 CPU system (dual core, non HT) C2 or C3 is generated
when both CPUs are in mwait state if this bit is set to 1. C2 or
C3 is determined by ARB_DIS = 0 or 1.
Mwait_4cpu_C23_en
4
0b
For 4 CPU system (dual core, HT) C2 or C3 is generated
when all 4 CPUs are in mwait state if this bit is set to 1. C2 or
C3 is determined by ARB_DIS = 0 or 1.
Reserved 7:5
000b