AMD SB600 User Manual

Page 14

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©2008 Advanced Micro Devices, Inc.

SATA Registers (Device 18, Function 0)

AMD SB600 Register Reference Manual

Proprietary

Page 14

Register Name

Offset Address

Serial ATA Capability Register 0

70h

Serial ATA Capability Register 1

74h

IDP Index

78h

IDP Data

7Ch

PHY Port0 Control

88h

PHY Port1 Control

8Ch

PHY Port2 Control

90h

PHY Port3 Control

94h

BIST pattern Count

C0h

PCI Target Control TimeOut Counter

C4h

Vendor ID - R - 16 bits - [PCI_Reg:00h]

Field Name

Bits

Default

Description

Vendor ID

15:0

1002h

This register holds a unique 16-bit value assigned to a vendor.
Combined with the device ID, it identifies any PCI device.

Device ID - R - 16 bits - [PCI_Reg:02h]

Field Name

Bits

Default

Description

Device ID

15:0

4380h

This register holds a unique 16-bit value assigned to a device.
Combined with the vendor ID, it identifies any PCI device.
4380h for the non-Raid5 controller
4381h for the Raid5 controller.
Bonding option default to the non-Raid 5 controller.

Command - RW - 16 bits - [PCI_Reg:04h]

Field Name

Bits

Default

Description

I/O Access Enable

0

0b

This bit controls access to the I/O space registers. When this
bit is 1, it enables the SATA controller to respond to PCI IO
space access.

Memory Access Enable

1

0b

This bit controls access to the memory space registers. When
this bit is 1, it enables the SATA controller to respond to PCI
memory space access

Bus Master Enable

2

0b

Bus master function enable.
1 = Enable
0 = Disable.

Special Cycle
Recognition Enable

3

0b

Read Only. Hardwired to ‘0’

Memory Write and
Invalidate Enable

4

0b

Read Only. Hardwired to ‘0’

VGA Palette Snoop
Enable

5

0b

Read Only. Hard-wired to ‘0’ indicating that the SATA host
controller does not need to snoop VGA palette cycles.

PERR- Detection Enable

6

0b

If set to 1, the IDE host controller asserts PERR- when it is the
agent receiving data AND it detects a parity error. PERR- is
not asserted if this bit is 0.

Wait Cycle Enable

7

0b

Read Only.
Hard-wired to ‘0’ to indicate that the SATA controller does not
need to insert a wait state between the address and data on
the AD lines.

SERR- Enable

8

0b

If set to 1, and bit 6 is set, then the SATA controller asserts
SERR- when it detects an address parity error. SERR- is not
asserted if this bit is 0.

Fast Back-to-Back
Enable

9

0b

Read Only. Hard-wired to ‘0’ to indicate that fast back to back
is only allowed to the same agent.

Interrupt Disable

10

0b

Complies with the PCI 2.3 specification.

Reserved 15:11

Reserved.

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