AMD SB600 - Manual (Page 178)

©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0)
AMD SB600 Register Reference Manual Proprietary Page 178
CLKVALUE - RW - 32 bits - [CpuControl:00h]
Field Name Bits Default Description
This register is located at the base address defined by CpuControl
PLvl2 - R - 8 bits - [CpuControl:04h]
Field Name Bits Default Description
PLvl2 7:0 00h Reads to this register return all zeros; writes to this register
have no effect. Reads to this register generates a “enter C2
power” to the clock control logic (STPCLK logic).
This register is located at the base address defined by CpuControl
PLvl3 – R – 8 bits - [CpuControl:05h]
Field Name Bits Default Description
PLvl3 7:0 00h Reads to this register return all zeros; writes to this register
have no effect. Reads to this register generates a “enter C3
power” to the clock control logic (STPCLK logic).
This register is located at the base address defined by CpuControl
PLvl4 – R - 8 bits - [CpuControl:06h]
Field Name Bits Default Description
PLvl4 7:0 00h Reads to this register return all zeros; writes to this register
have no effect. Reads to this register generates a “enter C4
power” to the clock control logic (STPCLK logic).
This register is located at the base address defined by CpuControl
AcpiSsCnt - RW - 8 bits - [AcpiSsCntBlk:00h]
Field Name Bits Default Description
AcpiSsCnt 0 0b Reserved
Reserved 7:1 00h
This register is located at the base address defined by AcpiSsCntBlk
EVENT_STATUS - RW - 32 bits - [AcpiGpe0Blk:00h]
Field Name Bits Default Description
GeventStatus 7:0 00h These bits indicate the status of the eight general purpose
event signals events to the SB
LEventStatus 8 0b This bit indicates the status of the legacy power management
logic implemented inside the SB.
TwarnStatus 9 0b This bit indicates the Temperature Caution input.
Reserved 10
USBStatus 11 0b This bit indicates the PME# from the internal USB controller
AC97Status 12 0b This bit indicates the PME# from the internal ac97 controller
OtherThermStatus 13 0b This bit indicates the status of OtherTherm from NB, fan, etc.
GPM9Status 14 0b This bit indicates the status of GPM[9] to SCI/Wakeup
PCIeHotPlugStatus 15 0b This bit indicates the status of PCIeHotPlug
ExtEvent0Status 16 0b This bit indicates the status of ExtEvent0 to SCI/Wakeup
ExtEvent1Status 17 0b This bit indicates the status of ExtEvent1 to SCI/Wakeup
PCIePmeStatus 18 0b This bit indicates the PME# from PCIExpress
GPM0Status 19 0b This bit indicates the status of GPM[0] to SCI/Wakeup
GPM1Status 20 0b This bit indicates the status of GPM[1] to SCI/Wakeup
GPM2Status 21 0b This bit indicates the status of GPM[2] to SCI/Wakeup
GPM3Status 22 0b This bit indicates the status of GPM[3] to SCI/Wakeup
GPM8Status 23 0b This bit indicates the status of GPM[8] to SCI/Wakeup
Gpio0Status 24 0b This bit indicates the status of GPIO0 (or WAKE#/GEVENT8
pin if PM IO Reg 84h bit1 =1) to SCI/wakeup
GPM4Status 25 0b This bit indicates the status of GPM[4] to SCI/Wakeup
GPM5Status 26 0b This bit indicates the status of GPM[5] to SCI/Wakeup