AMD SB600 - Manual (Page 203)

©2008 Advanced Micro Devices, Inc. AC ’97 Controller Functional Descriptions
AMD SB600 Register Reference Manual Proprietary Page 203
UnMask Latency Timer Expiration W - 32 bits - [PCI_Reg: 50h]
Field Name Bits Default Description
UnMask Latency Timer
Expiration 0 0b When this bit is set to 0, latency timer register will be ignored, and
AC97’s PCI master will not time out.
this bit is write-only, i.e., reading from it always returns 0.
Base1Enable 1 0b When set, Base 1 (offset 14h) becomes writeable.
ReqMask 2 0b This is for internal bus performance enhancement.
LargeMemEnable 3 0b When set, bits [13:8] of base 0 (offset 10h) becomes unwritable.
This is to cause OS to allocate wider memory map for ac97.
Reserved 31:4 0000_0
000h
2.5.1.2 Audio Memory Mapped Registers
All AC’97 controller audio registers are mapped to the memory.
Name Reg.
Interrupt 00h
Interrupt Enable 04h
Audio Command 08h
Output Phy Status and Address 0Ch
Input Phy Address & Data 10h
SLOTREQ 14h
Counter 18h
Input FIFO Threshold 1ch
Input DMA Link List Pointer 20h
Input DMA DT Start 24h
Input DMA DT Next 28h
Input DMA DT Current 2Ch
Input DT Size And FIFO Info 30h
Out DMA Slot Enbl. & Thresh 34h
Out DMA Link List Pointer 38h
Out DMA DT Start 3Ch
Out DMA DT Next 40h
Out DMA DT Current 44h
Out DMA DT Size and State 48h
SPDIF Command 4ch
SPDIF Link List Pointer 50h
SPDIF DT Start 54h
SPDIF DT Next 58h
SPDIF DT Current 5Ch
SPDIF DT Size & FIFO Info 60h
Modem Mirror 7Ch
Audio Mirror 80h
6-Channel Reorder Enable 84h
Audio FIFO Flush 88h
Output DMA FIFO Info 8Ch
SPDIF status bits reg1 90h
SPDIF status bits reg2 94h
SPDIF status bits reg3 98h
SPDIF status bits reg4 9Ch
SPDIF status bits reg5 A0h
SPDIF status bits reg6 A4h
Audio Phy Semaphore A8h