AMD SB600 User Manual
Page 278
©2008 Advanced Micro Devices, Inc.
GPIO/GPOC
AMD SB600 Register Reference Manual
Proprietary
Page 278
Pin Name
(Note 1)
Multi-function
Selection
Output Enable
(On SMBus
Controller)
Bus 00h/ Dev14h/
Fun00
Input if GPI
(On SMBus
Controller)
Bus 00h/
Dev14h/ Fun00
Output if GPO
(On SMBus
Controller)
Bus 00h/
Dev14h/ Fun00
Power
Domain
GPIO4/
SMARTVOLT/
SATA_IS2#
SMBus Reg5Eh[Bit 7]
0: GPIO if not used by
SATA
1: SMARTVOLT
RegA9h[Bit 0]
0: Output
1: Input (Tri-state)
*Note 2
RegAAh[Bit 0]
*Note 3
RegA8h[Bit 0]
S0
GPIO5/
SHUTDOWN#/
SMARTVOLT2
SMBus Reg9Ah[Bit7]
1 – SMARTVOLT2
0 – use
PMIO_59h[Bit5] to set
function
PM IO Reg59h[Bit 5]
0: GPIO
1: SHUTDOWN#
SMBus Reg9Ah[7]=0
RegA9h[Bit 1]
0: Output
1: Input (Tri-state)
*Note 2
RegAAh[Bit 1]
*Note 3
RegA8h[Bit 1]
S0
GPIO6/
GHI#/
SATA_IS1#
PM IO Reg60h[Bit 7]
0: GHI#
1: GPIO if not used by
SATA
RegA9h[Bit 2]
0: Output
1: Input (Tri-state)
*Note 2
RegAAh[Bit 2]
*Note 3
RegA8h[Bit 2]
S0
GPIO7/
WD_PWRGD
Strap on PCI AD [23]
0: GPIO
1: WD_PWRGD
RegA9h[Bit 3]
0: Output
1: Input (Tri-state)
*Note 2
RegAAh[Bit 3]
*Note 3
RegA8h[Bit 3]
S0
GPIO8/
DDC1_SDA
Input/Output pin only
Reg A9h[Bit 4]
0: Output
1: Input (Tri-state)
*Note 2
Reg AAh[Bit 4]
*Note 3
Reg A8h[Bit 4]
S0
GPIO9/
DDC1_SCL
Input/Output pin only
Reg A9h[Bit 5]
0: Output
1: Input (Tri-state)
*Note 2
Reg AAh[Bit 5]
*Note 3
Reg A8h[Bit 5]
S0
GPIO10/
SATA_IS0#
GPIO if not used by
SATA
Reg ABh[Bit 1]
0: Output
1: Input (Tri-state)
Reg ABh[Bit 2]
Reg ABh[Bit 0]
S0
GPIO11/
SPI_DO
SMBus RegABh[Bit 6]
0: SPI_DO
1: GPIO
Reg A9h[Bit 6]
0: Output
1: Input (Tri-state)
*Note 2
Reg AAh[Bit 6]
*Note 3
Reg A8h[Bit 6]
S0
GPIO12/
SPI_DI
SMBus RegABh[Bit 7]
0: SPI_DI
1: GPIO
Reg A9h[Bit 7]
0: Output
1: Input (Tri-state)
*Note 2
Reg AAh[Bit 7]
*Note 3
Reg A8h[Bit 7]
S0
GPIO13/
LAN_RST#
SMBus Reg83h[Bit 4]
0: LAN_RST#
1: GPIO
Reg 82h[Bit 4]
0: Output
1: Input (Tri-state)
Reg 83h[Bit 0]
Reg 82h[Bit 0]
S0
GPIO14/
ROM_RST#
SMBus Reg83h[Bit 5]
0: ROM_RST#
1: GPIO
Reg 82h[Bit 5]
0: Output
1: Input (Tri-state)
Reg 83h[Bit 1]
Reg 82h[Bit 1]
S0