AMD SB600 - Manual (Page 128)

©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0)
AMD SB600 Register Reference Manual Proprietary Page 128
Dma_Status- RW – 8 bits - [IO_Reg: 08h]
Field Name Bits Default Description
Dma_Status 7:0 00h Returns status when read; command for write
Dma_Status register
Dma_WriteRequest- RW – 8 bits - [IO_Reg: 09h]
Field Name Bits Default Description
Dma_WriteRequest 7:0 00h Request register.
Dma_WriteRequest register
Dma_WriteMask- RW – 8 bits - [IO_Reg: 0Ah]
Field Name Bits Default Description
Dma_WriteMask 7:0 00h Channel mask register.
Dma_WriteMask register
Dma_WriteMode- RW – 8 bits - [IO_Reg: 0Bh]
Field Name Bits Default Description
Dma_WriteMode 7:0 00h Mode register.
Dma_WriteMode register
Dma_Clear- RW – 8 bits - [IO_Reg: 0Ch]
Field Name Bits Default Description
Dma_Clear 7:0 00h Channel 0-3 DMA clear byte pointer
Dma_Clear register
Dma_MasterClr- RW – 8 bits - [IO_Reg: 0Dh]
Field Name Bits Default Description
Dma_MasterClr 7:0 00h Intermediate register.
Dma_MasterClr register
Dma_ClrMask- RW – 8 bits - [IO_Reg: 0Eh]
Field Name Bits Default Description
Dma_ClrMask 7:0 00h Channel 0-3 DMA Clear Mask
Dma_ClrMask register
Dma_AllMask- RW – 8 bits - [IO_Reg: 0Fh]
Field Name Bits Default Description
Dma_AllMask 7:0 00h Mask register.
Dma_AllMask register
IntrCntrl1Reg1- RW – 8 bits - [IO_Reg: 20h]
Field Name Bits Default Description
IntrCntrl1Reg1 7:0 00h IRQ0 – IRQ7:
Read IRR, ISR
Write ICW1, OCW2, OCW3
IntrCntrl1Reg1register