AMD SB600 User Manual

Page 19

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©2008 Advanced Micro Devices, Inc.

SATA Registers (Device 18, Function 0)

AMD SB600 Register Reference Manual

Proprietary

Page 19

MSI Control - RW- 32 bits - [PCI_Reg:50h]

Field Name

Bits

Default

Description

Capability ID

7:0

05h

Read-Only.
Capability ID. It indicates that this is and MSI capability ID.

Capability Next Pointer

15:8

70h

Read-Only.
Next Pointer (hard wired to 70h, points to Index Data pair
capability

Message Signaled
Interrupt Enable

16

0b

MSI Enable.

Multiple Message
Capable

19:17

010b

Multiple Message Capable.

Multiple Message Enable

22:20

000b

Multiple Message Enable.

MSI 64-bit Address

23

1b

Read-Only
Support 64-bit address.

Reserved 31:24

Reserved.

MSI Address - RW- 32 bits - [PCI_Reg:54h]

Field Name

Bits

Default

Description

Reserved 1:0

Reserved.

MSI Address

31:2

0000_0000h Lower 32 bits of the system specified message address

always DW aligned.

MSI Upper Address - RW- 32 bits - [PCI_Reg:58h]

Field Name

Bits

Default

Description

MSI Upper Address

31:0

0000_0000h Upper 32 bits of the system specified message address.

This register is optional and only implemented if
MC.C64=1.

MSI Data - RW- 16 bits - [PCI_Reg:5Ch]

Field Name

Bits

Default

Description

MSI Data

15:0

0000h

MSI Data

Power Management Capability ID - R- 16 bits - [PCI_Reg:60h]

Field Name

Bits

Default

Description

Capability ID

7:0

01h

Capability ID. Indicates this is power management capability
ID.

Capability Next Pointer

15:8

50h

Next Pointer.

Power Management Capability - R- 16 bits - [PCI_Reg:62h]

Field Name

Bits

Default

Description

Version

2:0

010b

Indicates support for Revision 1.1 of the PCI Power
Management Specification.

PME Clock

3

0b

Indicates that PCI clock is not required to generate PME#.

Reserved 4

Reserved

Device Specific
Initialization

5 1b

Indicates

whether

device-specific initialization is required.

Aux_Current

8:6

000b

Reports the maximum Suspend well current required when
in the D3

COLD

state. Hard wired to 000b.

D1_Support

9

0b

The D1 state is not supported.

D2_Support

10

0b

The D2 state is not supported.

PME_Support 15:11

00h

Read-Only.

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