AMD SB600 - Manual (Page 179)

©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0)
AMD SB600 Register Reference Manual Proprietary Page 179
EVENT_STATUS - RW - 32 bits - [AcpiGpe0Blk:00h]
Field Name Bits Default Description
AzaliaStatus 27 0b This bit indicates the status from the internal HD Audio
controller
GPM6Status 28 0b This bit indicates the status of GPM[6] to SCI/Wakeup
GPM7Status 29 0b This bit indicates the status of GPM[7] to SCI/Wakeup
A11: Gpio2Status
A12:
Gpio2Status/Gpio66Status 30 0b A11: This bit indicates the status of GPIO2 to SCI/wakeup
A12: This bit indicates the status of GPIO2 or GPIO66;
depending on PMIO_10h[7]. If PMIO_10h[7]=0, then it is
routed to GPIO2. If PMIO_10h[7]=1, then it is GPIO66
SataSciStatus 31 0b This bit indicates the status of SataSci to SCI/wakeup
This register is located at the base address defined by AcpiGpe0Blk.
EVENT_ENABLE - RW - 32 bits - [AcpiGpe0Blk:04h]
Field Name Bits Default Description
GeventEnable 7:0 00h These bits enable the GeventStatus to SCI output.
LeventEnable 8 0b This bit enables LEventStatus to SCI generation.
TwarnEnable 9 0b This bit enables TwarnStatus to SCI generation.
Reserved 10 0b
USBEnable 11 0b This bit enables PME# from the internal USB controllers
AC97Enable 12 0b This bit enables PME# from the internal ac97 controllers
OtherThermEnable 13 0b Enables bit for AcpiGpe0Blk, offset 00, bit 13
OtherThermStatus
GPM9Enable 14 0b Enables bit for AcpiGpe0Blk, offset 00, bit 14 GPM9Status
PCIeHotPlugEnable 15 0b Enable bit for AcpiGpe0Blk, offset 00, bit 15
PCIeHotPlugStatus
ExtEvent0Enable 16 0b Enables bit for AcpiGpe0Blk, offset 00, bit 16
ExtEvent0Status
ExtEvent1Enable 17 0b Enables bit for AcpiGpe0Blk, offset 00, bit 17
ExtEvent1Status
PCIePmeEnable 18 0b Enables bit for AcpiGpe0Blk, offset 00, bit 18 PCIePmeStatus
GPM0Enable 19 0b Enables bit for AcpiGpe0Blk, offset 00, bit 19 GPM0Status
GPM1Enable 20 0b Enables bit for AcpiGpe0Blk, offset 00, bit 20 GPM1Status
GPM2Enable 21 0b Enables bit for AcpiGpe0Blk, offset 00, bit 21 GPM2Status
GPM3Enable 22 0b Enables bit for AcpiGpe0Blk, offset 00, bit 22 GPM3Status
GPM8Enable 23 0b Enables bit for AcpiGpe0Blk, offset 00, bit 23 GPM8Status
Gpio0Enable 24 0b Enables bit for AcpiGpe0Blk, offset 00, bit 24 Gpio0Status
GPM4Enable 25 0b Enables bit for AcpiGpe0Blk, offset 00, bit 25 GPM4Status
GPM5Enable 26 0b Enables bit for AcpiGpe0Blk, offset 00, bit 26 GPM5Status
AzaliaEnable 27 0b Enables bit for AcpiGpe0Blk, offset 00, bit 27; for the internal
HD Audio PME
GPM6Enable 28 0b Enables bit for AcpiGpe0Blk, offset 00, bit 28 GPM6Status
GPM7Enable 29 0b Enables bit for AcpiGpe0Blk, offset 00, bit 29 GPM7Status
Gpio2Enable 30 0b Enables bit for AcpiGpe0Blk, offset 00, bit 30 Gpio2Status
SataSciEnable 31 0b Enables bit for AcpiGpe0Blk, offset 00, bit 31 SataSciStatus
This register is located at the base address defined by AcpiGpe0Blk.
SmiCmdPort - RW - 8 bits – [SmiCmdBlk: 00h]
Field Name Bits Default Description
SmiCmdPort 7:0 00h Used by BIOS and OS
This register is located at the base address defined by AcpiSmiCmd + offset 0.
SmiCmdStatus - RW - 8 bits – [SmiCmdBlk: 01h]
Field Name Bits Default Description
SmiCmdStatus 7:0 00h Used by BIOS and OS