AMD SB600 - Manual (Page 133)

©2008 Advanced Micro Devices, Inc. SMBus Module and ACPI Block (Device 20, Function 0)
AMD SB600 Register Reference Manual Proprietary Page 133
IntrCntrl2Reg1- RW – 8 bits - [IO_Reg: A0h]
Field Name Bits Default Description
IntrCntrl2Reg1 7:0 00h IRQ8 – IRQ15:
Read IRR, ISR
Write ICW1, OCW2, OCW3
IntrCntrl2Reg1 register
IntrCntrl2Reg2- RW – 8 bits - [IO_Reg: A1h]
Field Name Bits Default Description
IntrCntrl2Reg2 7:0 00h IRQ8 – IRQ15:
Read IMR
Write ICW2, ICW3, ICW4, OCW1
IntrCntrl2Reg2 register
Dma2_Ch4Addr - RW – 8 bits - [IO_Reg: C0h]
Field Name Bits Default Description
Dma2_Ch4Addr 7:0 00h DMA2 Ch4 Base and Current Address
Dma2_Ch4Addr register
Dma2_Ch4Cnt – RW – 8 bits - [IO_Reg: C2h]
Field Name Bits Default Description
Dma2_Ch4Cnt 7:0 00h DMA2 Ch4 Base and Current Count
Dma2_Ch4Cnt register
Dma2_Ch5Addr - RW – 8 bits - [IO_Reg: C4h]
Field Name Bits Default Description
Dma2_Ch5Addr 7:0 00h DMA2 Ch5 Base and Current Address
Dma2_Ch5Addr register
Dma2_Ch5Cnt - RW – 8 bits - [IO_Reg: C6h]
Field Name Bits Default Description
Dma2_Ch5Cnt 7:0 00h DMA2 Ch4 Base and Current Count
Dma2_Ch5Cnt register
Dma2_Ch6Addr - RW – 8 bits - [IO_Reg: C8h]
Field Name Bits Default Description
Dma2_Ch6Addr 7:0 00h DMA2 Ch6 Base and Current Address
Dma2_Ch6Addr register
Dma2_Ch6Cnt - RW – 8 bits - [IO_Reg: CAh]
Field Name Bits Default Description
Dma2_Ch6Cnt 7:0 00h DMA2 Ch6 Base and Current Count
Dma2_Ch6Cnt register
Dma2_Ch7Addr - RW – 8 bits - [IO_Reg: CCh]
Field Name Bits Default Description
Dma2_Ch7Addr 7:0 00h DMA2 Ch5 Base and Current Address
Dma2_Ch7Addr register