AMD SB600 - Manual (Page 41)

©2008 Advanced Micro Devices, Inc. SATA Registers (Device 18, Function 0)
AMD SB600 Register Reference Manual Proprietary Page 41
Port-N Serial ATA Error – RW – 32 bits [Mem_reg: ABAR + port offset + 30h]
Field Name Bits Default Description
ERROR 15:0 0000h The ERR field contains error information for use by host
software in determining the appropriate response to the error
condition.
15:12 Reserved
11
Internal Error (E): The host bus adapter
experienced an internal error that caused the
operation to fail and may have put the host bus
adapter into an error state. The internal error
may include a master or target abort when
attempting to access system memory, an
elasticity buffer overflow, a primitive mis-
alignment, a synchronization FIFO overflow, and
other internal error conditions. Typically when an
internal error occurs, a non-fatal or fatal status bit
in the PxIS register will also be set to give
software guidance on the recovery mechanism
required.
10
Protocol Error (P): A violation of the Serial ATA
protocol was detected.
9
Persistent Communication or Data Integrity
Error (C):
A communication error that was not
recovered occurred that is expected to be
persistent. Persistent communications errors
may arise from faulty interconnect with the
device, from a device that has been removed or
has failed, or a number of other causes.
8
Transient Data Integrity Error (T): A data
integrity error occurred that was not recovered by
the interface. This bit is set upon any error when
a Data FIS is received, including reception FIFO
overflow, CRC error or 10b8b decoding error.
7:2 Reserved
1
Recovered Communications Error (M):
Communications between the device and host
was temporarily lost but was re-established. This
can arise from a device temporarily being
removed, from a temporary loss of Phy
synchronization, or from other causes and may
be derived from the PhyNRdy signal between the
Phy and Link layers.
0
Recovered Data Integrity Error (I): A data
integrity error occurred that was recovered by the
interface through a retry operation or other
recovery action. This bit is set upon any error
when a Data FIS is received, including reception
FIFO overflow, CRC error or 10b8b decoding
error.
Write 1 to clear these bits.