AMD SB600 User Manual
Page 46
©2008 Advanced Micro Devices, Inc.
OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
Proprietary
Page 46
Device / Vendor ID – R - 32 bits - [PCI_Reg : 00h]
Field Name
Bits
Default
Description
DEV_ID
31:16
Function 0: 4387h
Function 1: 4388h
Function 2: 4389h
Function 3: 438Ah
Function 4: 438Bh
Device ID
Command – RW - 16 bits - [PCI_Reg : 04h]
Field Name
Bits
Default
Description
IO Space
Accesses
0
0b
A value of 0 disables the device response.
A value of 1 allows the device to respond to I/O Space accesses.
Memory Space
Accesses
1
0b
A value of 0 disables the device response.
A value of 1 allows the device to respond to Memory Space accesses.
Bus Master
2
0b
A value of 0 disables the device from generating PCI accesses.
A value of 1 allows the device to behave as a bus master.
Special Cycle
3
0b
Hard-wired to 0, indicating no Special Cycle support.
Memory Write
and Invalidate
Command
4
0b
When it is 0, Memory Write must be used.
When it is 1, masters may generate the command.
VGA Palette
Register
Accesses
5
0b
Hard-wired to 0, indicating the device should treat palette write accesses
like all other accesses.
Parity Enable
6
0b
When it is 1, the device must take its normal action when a parity error is
detected.
When it is 0, the device sets its Detected Parity Error status bit (bit 15 in
the Status register) when an error is detected, but continues normal
operations without asserting PERR#.
Reserved
7
0b
Hard-wired to 0 per PCI2.3 spec.
SERR# Enable
8
0b
A value of 0 disables the SERR# driver.
A value of 1 enables the SERR# driver.
Address parity errors are reported only if this bit and bit [6] are 1.
Fast Back-to-
Back Enable
9
0b
A value of 0 means that only fast back-to-back transactions to the same
agent are allowed.
A value of 1 means the master is allowed to generate fast back-to-back
transactions to different agents.
Interrupt Disable
10
0b
A value of 0 enables the assertion of the device/function’s INTx# signal.
A value of 1 disables the assertion of the device/function’s INTx# signal.
Reserved 15:11
Reserved
Status – R - 16 bits - [PCI_Reg : 06h]
Field Name
Bits
Default
Description
Reserved 2:0
Reserved
Interrupt Status
3
0b
This bit reflects the state of the interrupt in the device/function. Only
when the Interrupt Disable bit in the command register is a 0 and this
Interrupt Status bit is a 1 will the device’s/function’s INTx# signal be
asserted. Setting the Interrupt Disable bit to a 1 has no effect on the
state of this bit.
Capabilities List
4
1b
A value of 0 indicates that no New Capabilities linked list is available.
A value of 1 indicates that the value read at offset 34h is a pointer in
Configuration Space to a linked list of new capabilities.
66 MHz Capable
5
1b
Hard-wired to 1, indicating 66MHz capable.
Reserved 6
Reserved
Fast Back-to-
Back Capable
7
1b
Hard-wired to 1, indicating Fast Back-to-Back capable.