AMD SB600 - Manual (Page 283)

©2008 Advanced Micro Devices, Inc. GEVENT/GPE/GPM/ExtEvent
AMD SB600 Register Reference Manual Proprietary Page 283
4.2 GEVENT/GPE/GPM/ExtEvent
4.2.1 GEVENT as GPIO
GEVENT[1:0] are inputs only. Their status can be read from PM I/O Reg 92h Bit[1:0].
GEVENT[7:2] can be programmed either as GPIO lines or as GPE lines (see section 4.2.2 ).
ƒ PM I/O Reg 91h Bit[7:2] defines GEVENT[7:2] pins as output or input
ƒ 0: Enable output
ƒ 1: Tris-tate (input)
ƒ For GEVENT pins defined as output, PM I/O Reg 90h Bit[7:2] sets the output value
ƒ 0: Output low
ƒ 1: Output high
ƒ For GEVENT pins defined as input, PM I/O Reg 92h Bit[7:2] are used to read the input status.
GEVEN8 can be programmed either as GPIO line or as GPE line (see section 4.2.2 ).
ƒ PM I/O Reg 84h Bit[3] defines GEVENT8 pins as output or input
ƒ 0: Enable output
ƒ 1: Tris-tate (input)
ƒ For GEVENT8 pin defined as output, PM I/O Reg 84h Bit[2] sets the output value
ƒ 0: Output low
ƒ 1: Output high
ƒ For GEVENT8 pin defined as input, PM I/O Reg 84h Bit[4] is used to read the input status.
4.2.2 General Purpose Event (GPE)
The General Purpose Event (GPE) pins can generate wake events, SCI, SMI#, SMI# followed by SCI, or
IRQ13.
When not used as GPE pins, these pins may also be used as GPIO pins as described in sections 4.1.1 ,
4.2.1 , 4.2.3 , 4.2.4 .
The GPE pins include:
ƒ GEVENT[8:0]
ƒ GPM[9:0]
ƒ EXTEVENT[1:0]
ƒ GPIO0, GPIO2, GPIO64
Table 4-3: GPE Pins
Pin Name
(*Note 1) Multi-Function
Selection Configure Bit
00 – SCI or SMI#
01 – SMI#
10 – SMI#
followed by SCI
11 - IRQ13
Trigger Configure
0–Falling edge
1–Rising edge
Enable
ACPI Event Status
(Write 1 to ACPI
GPE00h Bit to
Clear) Power
Domain
GEVENT0/
GA20IN SMBus
Reg64h[Bit11]
0: GEVENT0
1: GA20IN PM IO
Reg30h[Bit1:0] PM IO
Reg36h[Bit 0] ACPI
GPE04h[Bit 0] PM IO
Reg39h[Bit 0]
or ACPI
GPE00h[Bit0] S0
GEVENT1/
KBRST# SMBus
Reg64h[Bit9]
0: KBRST#
1: GEVENT1 PM IO
Reg30h[Bit3:2] PM IO
Reg36h[Bit 1] ACPI
GPE04h[Bit 1] PM IO
Reg39h[Bit 1]
or ACPI
GPE00h[Bit 1] S0