Rockwell Automation 1785-BCM_BEM, D17856.5.4 PLC-5 Backup Communication Module User Manual - Manual (Page 103)

Programming Techniques
Chapter 7
7-6
Method 2 — Transferring Data Multiple Blocks at a Time
In the second method, transferring data multiple blocks at a time, the
application program takes advantage of the PLC-5 block transfer queue.
Because the PLC-5 processor assigns the task of block transfer to one
microprocessor and program scan to another, block transfers are executed
asynchronously and simultaneously in relation to the scanning of the program,
permitting multiple block transfers per scan.
Using the multiple-blocks-at-a-time method, the primary system transfers
various blocks in the same scan. The secondary system checks the transfer after
the primary system sends the entire segment. Using this method, the application
program of the primary PLC-5/15 or PLC-5/25 processor can contain up to 16
BTW instructions and 1 BTR instruction. The application program of the
secondary PLC-5/15 or PLC-5/25 processor can contain up to 16 BTR
instructions and 1 BTW instruction.
Note that this method of transfer is suitable in cases where you want to transfer
no more than 992 words of data. This number refers to the number of
block-transfer requests in the same chassis (16) times the number of words
transferred in each data block (62).
If you use a PLC-5/20, -5/30, -5/40, -5/60, or -5/80 processor, the application
program of the primary processor can contain up to 64 BTW instructions and 1
BTR instruction. The application program of the secondary processor can
contain up to 64 BTR instructions and 1 BTW instruction.
In this case, you can start the transfer of up to 3968 words of data in one single
scan. This number refers to the number of block transfer requests in the same
chassis (64) time the number of words transferred in each data block (62).
In the following paragraphs, we explain how this method works for a program
where:
the primary processor has 3 BTW instructions and 1 BTR instruction enabled
the secondary processor has 3 BTR instruction and 1 BTW instruction
enabled
Program operation varies depending on if the system is primary or secondary.