Timing diagrams, Timing diagrams -20 – KEYENCE LK-CC100/DN100 User Manual
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3
3 Connecting to DeviceNet
Timing Diagrams
This is the timing diagram for a control input.
• OUT: Master
slave
• IN: Slave
master
• Internal: Internal processing at the slave
• Control inputs that do not have the ***_STATE flag follow the same timing except that the ***_STATE
flag is omitted.
• The X axis shows the correct timing but not the exact time.
Normal timing (status change from OFF
ON)
Abnormal timing (error, status stays ON)
Reference
1 ***_REQ
OUT
3 ***_ACQ
Verify ***_ACQ is OFF, then turn ***_REQ ON.
IN
4 ***_ERR
IN
5 ***_STATE IN
2 Internal
processing
1 ***_REQ
OUT
3 ***_ACQ
IN
4 ***_ERR
IN
5 ***_STATE IN
2 Internal
processing
Issue the next ***_REQ after
verifying ***_ACQ has gone LO.
***_ACQ turns ON after
***_ERR changes state.
***_STATE does not change if ***_ERR goes to HI
because no processing is performed.
***_ERR changes to the OFF state at the
same time ***_ACQ turns OFF.
Verify ***_ACQ is OFF, then turn ***_REQ ON.