Motorola ColdFire MCF5281 - Manual (Page 238)

External Interface Module (EIM)
13-14 Freescale Semiconductor
Figure 13-18. Line Write Burst-Inhibited
13.5 Misaligned Operands
Because operands can reside at any byte boundary, unlike opcodes, they are allowed to be misaligned. A
byte operand is properly aligned at any address, a word operand is misaligned at an odd address, and a
longword is misaligned at an address not a multiple of four. Although the processor enforces no alignment
restrictions for data operands (including program counter (PC) relative data addressing), additional bus
cycles are required for misaligned operands.
Instruction words and extension words (opcodes) must reside on word boundaries. Attempting to prefetch
a misaligned instruction word causes an address error exception.
The processor converts misaligned, cache-inhibited operand accesses to multiple aligned accesses.
Figure 13-19 shows the transfer of a longword operand from a byte address to a 32-bit port. In this
example, SIZ[1:0] specify a byte transfer and a byte offset of 0x1. The slave device supplies the byte and
acknowledges the data transfer. When the processor starts the second cycle, SIZ[1:0] specify a word
transfer with a byte offset of 0x2. The next two bytes are transferred in this cycle. In the third cycle, byte
3 is transferred. The byte offset is now 0x0, the port supplies the final byte, and the operation is complete.
Figure 13-19. Example of a Misaligned Longword Transfer (32-Bit Port)
If an operand is cacheable and is misaligned across a cache-line boundary, both lines are loaded into the
cache. The example in
Figure 13-20 differs from that in Figure 13-19 in that the operand is word-sized and
the transfer takes only two bus cycles.
A[31:0]
R/W, TIP
SIZ[1:0]
TS
D[31:0]
TA
Line Longword
Basic Fast Fast Fast
A[3:2] = 00 A[3:2] = 01 A[3:2] = 10 A[3:2] = 11
Write Write Write Write
S0 S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5
CLKOUT
CSn
OE, BSn
Transfer 1
Transfer 2
Transfer 3
—
—
Byte 3
Byte 0
—
—
—
Byte 1
—
—
Byte 2
—
31 24 23 16 15 8 7 0
001
010
100
A[2:0]
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3