4 receive descriptor active register (rdar), 4 receive descriptor active register (rdar) -11 – Motorola ColdFire MCF5281 User Manual
Page 321
Fast Ethernet Controller (FEC)
Freescale Semiconductor
17-11
17.4.4
Receive Descriptor Active Register (RDAR)
RDAR is a command register, written by the user, indicating the receive descriptor ring is updated (the
driver produced empty receive buffers with the empty bit set).
When the register is written, the RDAR bit is set. This is independent of the data actually written by the
user. When set, the FEC polls the receive descriptor ring and processes receive frames (provided
ECR[ETHER_EN] is also set). After the FEC polls a receive descriptor whose empty bit is not set, FEC
clears the RDAR bit and ceases receive descriptor ring polling until the user sets the bit again, signifying
that additional descriptors are placed into the receive descriptor ring.
The RDAR register is cleared at reset and when ECR[ETHER_EN] is cleared.
IPSBAR
Offset:
0x1008
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
HB
ERR
BABR BABT GRA
TXF
TXB
RXF
RXB
MII
EB
ERR
LC
RL
UN
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 17-3. Ethernet Interrupt Mask Register (EIMR)
Table 17-6. EIMR Field Descriptions
Field
Description
31–19
See
and
Interrupt mask. Each bit corresponds to an interrupt source defined by the EIR register. The corresponding
EIMR bit determines whether an interrupt condition can generate an interrupt. At every processor clock, the
EIR samples the signal generated by the interrupting source. The corresponding EIR bit reflects the state of
the interrupt signal even if the corresponding EIMR bit is set.
0 The corresponding interrupt source is masked.
1 The corresponding interrupt source is not masked.
18–0
Reserved, must be cleared.
IPSBAR
Offset:
0x1010
Access: User read/write
31 30 29 28 27 26 25
24
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R 0 0 0 0 0 0 0
RDAR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17-4. Receive Descriptor Active Register (RDAR)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3