Motorola ColdFire MCF5281 - Manual (Page 351)

Fast Ethernet Controller (FEC)
Freescale Semiconductor 17-41
17.5.11 Full Duplex Flow Control
Full-duplex flow control allows you to transmit pause frames and to detect received pause frames. Upon
detection of a pause frame, MAC data frame transmission stops for a given pause duration.
To enable PAUSE frame detection, the FEC must operate in full-duplex mode (TCR[FDEN] set) with flow
control (RCR[FCE] set). The FEC detects a pause frame when the fields of the incoming frame match the
pause frame specifications, as shown in
Table 17-38 . In addition, the receive status associated with the
frame should indicate that the frame is valid.
The receiver and microcontroller modules perform PAUSE frame detection. The microcontroller runs an
address recognition subroutine to detect the specified pause frame destination address, while the receiver
detects the type and opcode pause frame fields. On detection of a pause frame, TCR[GTS] is set by the
FEC internally. When transmission has paused, the EIR[GRA] interrupt is asserted and the pause timer
begins to increment. The pause timer uses the transmit backoff timer hardware for tracking the appropriate
collision backoff time in half-duplex mode. The pause timer increments once every slot time, until
OPD[PAUSE_DUR] slot times have expired. On OPD[PAUSE_DUR] expiration, TCR[GTS] is cleared
allowing MAC data frame transmission to resume. The receive flow control pause status bit
(TCR[RFC_PAUSE]) is set while the transmitter pauses due to reception of a pause frame.
To transmit a pause frame, the FEC must operate in full-duplex mode and you must set flow control pause
(TCR[TFC_PAUSE]). After TCR[TFC_PAUSE] is set, the transmitter sets TCR[GTS] internally. When
the transmission of data frames stops, the EIR[GRA] (graceful stop complete) interrupt asserts and the
pause frame is transmitted. TCR[TFC_PAUSE,GTS] are then cleared internally.
You must specify the desired pause duration in the OPD register.
FDFF_FFFF_FFFF 0x3C 60
DDFF_FFFF_FFFF 0x3D 61
9DFF_FFFF_FFFF 0x3E 62
BDFF_FFFF_FFFF 0x3F 63
Table 17-38. PAUSE Frame Field Specification
48-bit Destination Address 0x0180_C200_0001 or Physical Address
48-bit Source Address Any
16-bit Type 0x8808
16-bit Opcode
0x0001
16-bit PAUSE Duration 0x0000 – 0xFFFF
Table 17-37. Destination Address to 6-Bit Hash (continued)
48-bit DA
6-bit Hash
(in hex)
Hash Decimal
Value
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3