Motorola ColdFire MCF5281 - Manual (Page 488)

FlexCAN
25-18 Freescale Semiconductor
25.5.1 CAN Module Configuration Register (CANMCR)
Table 25-8 describes the CANMCR fields.
15 14 13 12 11 10 9 8
Field STOP FRZ — HALT NOTRDY WAKEMSK SOFTRST FRZACK
Reset 0101_1001
R/W R/W
7 6 5 4 3 0
Field SUPV SELFWAKE APS STOPACK —
Reset 1000_0000
R/W R/W
Address IPSBAR + 0x1C_0000
Figure 25-6. CAN Module Configuration Register (CANMCR)
Table 25-8. CANMCR Field Descriptions
Bits Name Description
15 STOP
Low-power stop mode enable. The STOP bit may only be set by the CPU. It may be cleared either
by the CPU or by the FlexCAN, if the SELFWAKE bit is set.
0 Enable FlexCAN clocks
1 Disable FlexCAN clocks
14 FRZ
FREEZE assertion response. When FRZ = 1, the FlexCAN can enter debug mode when the BKPT
line is asserted or the HALT bit is set. Clearing this bit field causes the FlexCAN to exit debug
mode. Refer to
Section 25.4.11.1, “Debug Mode ” for more information.
0 FlexCAN ignores the BKPT signal and the HALT bit in the module configuration register.
1 FlexCAN module enabled to enter debug mode.
13 — Reserved
12 HALT
Halt FlexCAN S-Clock. Setting the HALT bit has the same effect as assertion of the BKPT signal
on the FlexCAN without requiring that BKPT be asserted. This bit is set to one after reset. It should
be cleared after initializing the message buffers and control registers. FlexCAN message buffer
receive and transmit functions are inactive until this bit is cleared.
When HALT is set, write access to certain registers and bits that are normally read-only is allowed.
0 The FlexCAN operates normally
1 FlexCAN enters debug mode if FRZ = 1
11 NOTRDY
FlexCAN not ready. This bit indicates that the FlexCAN is either in low-power stop mode or debug
mode. This bit is read-only and is set only when the FlexCAN enters low-power stop mode or
debug mode. It is cleared once the FlexCAN exits either mode, either by synchronization to the
CAN bus or by the self-wake mechanism.
0 FlexCAN has exited low-power stop mode or debug mode.
1 FlexCAN is in low-power stop mode or debug mode.
10
WAKEMS
K
Wakeup interrupt mask. The WAKEMSK bit enables wake-up interrupt requests.
0 Wake up interrupt is disabled.
1 Wake up interrupt is enabled.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3