9 status register (sr) – Motorola ColdFire MCF5281 User Manual
Page 54
ColdFire Core
2-8
Freescale Semiconductor
2.2.9
Status Register (SR)
The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control
bits. In supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits (CCR) are
accessible. The control bits indicate the following states for the processor: trace mode (T bit), supervisor
or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access
when in supervisor mode. The lower byte of the SR (the CCR) must be loaded explicitly after reset and
before any compare (CMP), Bcc, or Scc instructions execute.
BDM: 0x80E (SR)
Access: Supervisor read/write
BDM read/write
System Byte
Condition Code Register (CCR)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
T
0
S
M
0
I
0
0
0
X
N
Z
V
C
W
Reset
0
0
1
0
0
1
1
1
0
0
0
—
—
—
—
—
Figure 2-8. Status Register (SR)
Table 2-3. SR Field Descriptions
Field
Description
15
T
Trace enable. When set, the processor performs a trace exception after every instruction.
14
Reserved, must be cleared.
13
S
Supervisor/user state.
0 User mode
1 Supervisor mode
12
M
Master/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or
move to SR instructions.
11
Reserved, must be cleared.
10–8
I
Interrupt level mask. Defines current interrupt level. Interrupt requests are inhibited for all priority levels less than or
equal to current level, except edge-sensitive level 7 requests, which cannot be masked.
7–0
CCR
Refer to
Section 2.2.4, “Condition Code Register (CCR)”
.
2.2.10
Memory Base Address Registers (RAMBAR, FLASHBAR)
The memory base address registers are used to specify the base address of the internal SRAM and flash
modules and indicate the types of references mapped to each. Each base address register includes a base
address, write-protect bit, address space mask bits, and an enable bit. FLASHBAR determines the base
address of the on-chip flash, and RAMBAR determines the base address of the on-chip RAM. For more
information, refer to
Section 5.3.1, “SRAM Base Address Register (RAMBAR)”
“Flash Base Address Register (FLASHBAR)”
.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3