Motorola ColdFire MCF5281 - Manual (Page 657)

Debug Support
Freescale Semiconductor 30-39
complete before freeing the local bus for the debug module to perform its access. After the debug module
bus cycle, the processor reclaims the bus.
Breakpoint registers must be carefully configured in a development system if the processor is executing.
The debug module contains no hardware interlocks, so TDR should be disabled while breakpoint registers
are loaded, after which TDR can be written to define the exact trigger. This prevents spurious breakpoint
triggers.
Because there are no hardware interlocks in the debug unit, no BDM operations are allowed while the CPU
is writing the debug’s registers (DSCLK must be inactive).
Note that the debug module requires the use of the internal bus to perform BDM commands. In Revision
A, if the processor is executing a tight loop that is contained within a single aligned longword, the
processor may never grant the internal bus to the debug module, for example:
align4
label1: nop
bra.b label1
or
align4
label2: bra.w label2
The processor grants the internal bus if these loops are forced across two longwords.
30.7 Processor Status, DDATA Definition
This section specifies the ColdFire processor and debug module’s generation of the processor status (PST)
and debug data (DDATA) output on an instruction basis. In general, the PST/DDATA output for an
instruction is defined as follows:
PST = 0x1, {PST = [0x89B], DDATA= operand}
where the {...} definition is optional operand information defined by the setting of the CSR.
The CSR provides capabilities to display operands based on reference type (read, write, or both). A PST
value {0x8, 0x9, or 0xB} identifies the size and presence of valid data to follow on the DDATA output {1,
2, or 4 bytes}. Additionally, for certain change-of-flow branch instructions, CSR[BTB] provides the
capability to display the target instruction address on the DDATA output {2, 3, or 4 bytes} using a PST
value of {0x9, 0xA, or 0xB}.
30.7.1 User Instruction Set
Table 30-22 shows the PST/DDATA specification for user-mode instructions. Rn represents any {Dn, An}
register. In this definition, the ‘y’ suffix generally denotes the source and ‘x’ denotes the destination
operand. For a given instruction, the optional operand data is displayed only for those effective addresses
referencing memory. The ‘DD’ nomenclature refers to the DDATA outputs.
Table 30-22. PST/DDATA Specification for User-Mode Instructions
Instruction Operand Syntax PST/DDATA
add.l <ea>y,Rx PST = 0x1, {PST = 0xB, DD = source operand}
add.l Dy,<ea>x PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
addi.l #imm,Dx PST = 0x1
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3