Motorola ColdFire MCF5281 - Manual (Page 665)

Freescale Semiconductor 31-1
Chapter 31
IEEE 1149.1 Test Access Port (JTAG)
The Joint Test Action Group, or JTAG, is a dedicated user-accessible test logic, that complies with the
IEEE 1149.1 standard for boundary-scan testability, to help with system diagnostic and manufacturing
testing.
This architecture provides access to all data and chip control pins from the board-edge connector through
the standard four-pin test access port (TAP) and the JTAG reset pin, TRST.
Figure 31-1 shows the block diagram of the JTAG module.
Figure 31-1. JTAG Block Diagram
4-BIT TAP INSTRUCTION REGISTER
3 0
1-BIT BYPASS REGISTER
148-BIT BOUNDARY SCAN REGISTER
32-BIT IDCODE REGISTER
TRST/DSCLK
TCLK
TMS/BKPT
0 31
0 147
TAP CONTROLLER
TDI/DSI
1
0
TDO/DSO
JTAG Module
to Debug Module
7-BIT JTAG_CFM_CLKDIV REGISTER
0 6
3-BIT TEST_CTRL REGISTER
0 2
4-BIT TAP INSTRUCTION DECODER
1
0
Disable DSCLK
Force BKPT = 1
DSI = 0
JTAG_EN
DSO
DSI
BKPT
DSCLK
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3