Agilent Technologies E1300B - Manual (Page 120)

Standard Event Status
Register
The Standard Event Status Register in the Standard Event status group
monitors the instrument status events shown in Table 4-2. When one of these
events occurs, it sets a corresponding bit in the Standard Event Status Register.
NOTE The Standard Event Status Register bits are not reported in the Status Byte
Register unless unmasked by the Standard Event Status Enable Register. Refer
to the section "Unmasking Standard Event Status Bits" for more information.
Table 4-2. Standard Event Status Register
Bit
Number
Decimal
Weight Description
0 1 O peration Complete. The instrument has completed all pending
operations. This bit is set in response to the *O PC command.
1 2 Request Control. An instrument is requesting permission to become
the active G PIB controller.
2 4 Q uery Error. A problem has occurred in the instrument’s output
queue.
3 8 D evice D ependent Error. An instrument operation did not
complete possibly because of an abnormal hardware or firmware
condition (overload occurred, self-test failure, loss of calibration
or configuration memory, etc.)
4 16 Execution Error. The instrument cannot do the operation(s)
requested by a command.
5 32 Command Error. The instrument cannot understand or execute the
command.
6 64 U ser Request. The instrument is under local (front panel) control.
7 128 Power-O n. Power has been applied to the instrument. You must
execute the *PSC 0 command to the System Instrument to allow
this bit to remain enabled when power is cycled. See the *PSC
command later in this chapter for an example.
8-15 Reserved for future use (always return zero).
Unmasking Standard
Event Status Bits
To allow any of the Standard Event Status register bits to set bit 5 (ESB) of the
Status Byte register, you must first unmask the bit(s) using the Standard Event
Status Enable register with the command:
* ESE
For example, suppose your application requires an interrupt whenever any type
of error occurs. The error related bits in the Standard Event Status register are
bits 2 through 5. The sum of the decimal weights of these bits is 60. You can
enable any one of these bits to set bit 5 in the Status Byte Register by sending:
* ESE 60
If you want to generate a service request following any one of these errors, you
can do so by unmasking bit 5 (ESB) in the Status Byte register:
* SRE 32
* ESE 60
Now, whenever an error occurs, it will set one of the bits 2 - 5 in the Standard
Event Status register which will set bit 5 in the Status Byte register. Since bit 5 is
6-6 Controlling Instruments Using GPIB