Altera Low Latency Ethernet 10G MAC - Manual (Page 2)

Contents
About LL Ethernet 10G MAC............................................................................. 1-1
Features......................................................................................................................................................... 1-2
Release Information.....................................................................................................................................1-3
Device Family Support................................................................................................................................1-3
Definition: Device Support Level...................................................................................................1-4
Performance and Resource Utilization.....................................................................................................1-4
Resource Utilization........................................................................................................................ 1-4
TX and RX Latency..........................................................................................................................1-5
Getting Started with LL Ethernet 10G MAC...................................................... 2-1
Introduction to Altera IP Cores.................................................................................................................2-1
Installing and Licensing IP Cores..............................................................................................................2-2
Specifying IP Core Parameters and Options............................................................................................2-2
Parameterizing the IP Core........................................................................................................................ 2-3
Parameter Settings....................................................................................................................................... 2-4
Generated Files.............................................................................................................................................2-6
Simulating Altera IP Cores in other EDA Tools..................................................................................... 2-7
Upgrading Outdated IP Cores................................................................................................................... 2-8
Migrating IP Cores to a Different Device.................................................................................................2-9
Design Considerations.............................................................................................................................. 2-11
Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC.................................2-11
Timing Constraints........................................................................................................................2-12
Functional Description of LL Ethernet 10G MAC............................................. 3-1
Architecture.................................................................................................................................................. 3-1
Interfaces....................................................................................................................................................... 3-2
Frame Types..................................................................................................................................................3-4
TX Datapath................................................................................................................................................. 3-4
Padding Bytes Insertion.................................................................................................................. 3-4
Address Insertion.............................................................................................................................3-4
CRC-32 Insertion.............................................................................................................................3-5
XGMII Encapsulation..................................................................................................................... 3-6
Inter-Packet Gap Generation and Insertion................................................................................ 3-7
XGMII Transmission...................................................................................................................... 3-7
Unidirectional Feature.................................................................................................................... 3-8
TX Timing Diagrams.......................................................................................................................3-9
RX Datapath............................................................................................................................................... 3-13
XGMII Decapsulation................................................................................................................... 3-13
CRC Checking................................................................................................................................3-13
Address Checking.......................................................................................................................... 3-14
Frame Type Checking................................................................................................................... 3-14
TOC-2 Low Latency Ethernet 10G MAC User Guide
Altera Corporation