Altera Low Latency Ethernet 10G MAC - Manual (Page 70)

Word
Offset
Register Name Description Access HW Reset
Value
0x00FC
rx_pktovrflow_error
36-bit error counter that collects the
number of RX frames that are truncated
when a FIFO buffer overflow persists:
• 0x00FC = Lower 32 bits of the error
counter.
• 0x00FD = Upper 4 bits of the error
counter occupy bits [3:0]. Bits [31:4] are
unused.
To read the counter, read the lower 32 bits
followed by the upper 4 bits. The IP core
clears the counter after a read.
RO 0x0
0x00FD
0x00FE
rx_pktovrflow_
etherStatsDropEvents
36-bit error counter that collects the
number of RX frames that are dropped
when FIFO buffer overflow persists:
• 0x00FE = Lower 32 bits of the error
counter.
• 0x00FF = Upper 4 bits of the error
counter occupy bits [3:0]. Bits [31:4] are
unused.
To read the counter, read the lower 32 bits
followed by the upper 4 bits. The IP core
clears the counter after a read.
RO 0x0
0x00FF
Related Information
• Length Checking on page 3-14
• Statistics Registers on page 4-25
TX Timestamp Registers
The TX timestamp registers are used when you turn on Enable time stamping. They are reserved when
not used.
4-18 TX Timestamp Registers
UG-01144
2014.12.15
Altera Corporation Configuration Registers for LL Ethernet 10G MAC
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