Altera Low Latency Ethernet 10G MAC - Manual (Page 58)

Table 4-5: MAC Reset Control Register
Word
Offset
Register Name Description Access HW Reset
Value
0x001F
mac_reset_control
The user application can use the specified bits
in this register to reset the MAC datapaths. The
effect is the same as asserting the
tx_rst_n
or
rx_rst_n
signals.
• Bit 0—TX datapath reset.
0: Stops the reset process.
1: Starts the reset process.
• Bits 7:1—reserved.
• Bit 8—RX datapath reset.
0: Stops the reset process.
1: Starts the reset process.
• Bits 31:9—reserved.
RW 0x0
TX_Configuration and Status Registers
Table 4-6: TX Configuration and Status Registers
Word
Offset
Register Name Description Access HW Reset
Value
0x0020
tx_packet_control • Bit 0—configures the TX path.
0: Enables the TX path.
1: Disables the TX path. The MAC IP core
indicates a backpressure on the Avalon-ST
transmit data interface by deasserting the
avalon_st_tx_ready
signal. When
disabled, the IP core stops generating new
pause and PFC frames.
• Bits 31:1—reserved.
You can change the value of this register as
necessary. If the TX path is disabled while a
frame is being transmitted, the MAC IP core
completes the transmission before disabling
the TX path.
RW 0x0
4-6 TX_Configuration and Status Registers
UG-01144
2014.12.15
Altera Corporation Configuration Registers for LL Ethernet 10G MAC
Send Feedback