Altera Low Latency Ethernet 10G MAC - Manual (Page 20)

6. To regenerate the new IP variation for the new target device, click Generate. When generation is
complete, click Close.
7. Click Finish to complete migration of the IP core. Click OK if you are prompted to overwrite IP core
files. The Device Family column displays the new target device name when migration is complete. The
migration process replaces <my_ip> .qip with the <my_ip> .qsys top-level IP file in your project.
Note: If migration does not replace <my_ip>
.qip with <my_ip> .qsys , click Project > Add/Remove
Files in Project to replace the file in your project.
8. Review the latest parameters in the parameter editor or generated HDL for correctness. IP migration
may change ports, parameters, or functionality of the IP core. During migration, the IP core's HDL
generates into a library that is different from the original output location of the IP core. Update any
assignments that reference outdated locations. If your upgraded IP core is represented by a symbol in a
supporting Block Design File schematic, replace the symbol with the newly generated <my_ip> .bsf
after migration.
Note: The migration process may change the IP variation interface, parameters, and functionality.
This may require you to change your design or to re-parameterize your variant after the
Upgrade IP Components dialog box indicates that migration is complete. The Description
field identifies IP cores that require design or parameter changes.
Related Information
Altera IP Release Notes
Design Considerations
Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC
Altera recommends the following migration path. Migrating your existing design in this manner allows
you to take advantage of the benefits of LL Ethernet 10G MAC—low resource count and low latency.
Migration—32-bit Datapath on Avalon-ST Interface
This migration path implements 32-bit datapath on the Avalon ST and Avalon-MM interfaces.
1. Instantiate the LL Ethernet 10G MAC IP core in your design. If you are using a PHY with 64-bit SDR
XGMII interface, turn on the Use legacy Ethernet 10G MAC XGMII Interface option.
2. Modify your user logic to accommodate 32-bit datapaths on Avalon-ST TX and RX data interfaces.
3. Ensure that
tx_312_5_clk
and
rx_312_5_clk
are connected to 312.5-MHz clock sources. Altera
recommends that you use the same clock source for these clock signals.
4. Update the register offsets to the offsets of the LL Ethernet 10G MAC. The configuration registers of
the LL Ethernet 10G MAC allow access to new features such as error correction and detection on
memory blocks.
5. If you turn on the Use legacy Ethernet 10G MAC XGMII Interface option, add a 156.25 MHz clock
source for
tx_156_25_clk
and
rx_156_25_clk
. This 156.25 MHz clock source must be rise-to-rise
synchronous to the 312.5 MHz clock source.
6. Ensure that
csr_clk
is within 125 MHz to 156.25 MHz. Otherwise, some statistic counters may not be
accurate.
UG-01144
2014.12.15
Design Considerations 2-11
Getting Started with LL Ethernet 10G MAC Altera Corporation
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