Altera Low Latency Ethernet 10G MAC - Manual (Page 71)

Table 4-10: TX Timestamp Registers
Word
Offset
Register Name Description Access HW Reset
Value
0x0100
tx_period_10G Specifies the clock period for the
timestamp adjustment on the TX datapath
for 10G operations. The MAC IP core
multiplies the value of this register by the
number of stages separating the actual
timestamp and XGMII bus.
• Bits 15:0—period in fractional
nanoseconds.
• Bits 19:16—period in nanoseconds.
• Bits 31:20—reserved. Set these bits to 0.
The default value is 3.2 ns for 312.5 MHz
clock. Configure this register before you
enable the MAC IP core for operations.
RW 0x33333
0x0102
tx_fns_adjustment_10G
Static timing adjustment in fractional
nanoseconds on the TX datapath for 10G
operations.
• Bits 15:0—adjustment period in
fractional nanoseconds.
• Bits 31:16—reserved. Set these bits to 0.
Configure this register before you enable
the MAC IP core for operations.
RW 0x0
0x0104
tx_ns_adjustment_10G
Static timing adjustment in nanoseconds
on the TX for 10G operations.
• Bits 15:0—adjustment period in
nanoseconds.
• Bits 31:16—reserved. Set these bits to 0.
Configure this register before you enable
the MAC IP core for operations.
RW 0x0
0x0108
tx_period_mult_speed Specifies the clock period for timestamp
adjustment on the TX datapath for 10M/
100M/1G operations. The MAC IP core
multiplies the value of this register by the
number of stages separating the actual
timestamp and GMII/MII bus.
• Bits 15:0—period in fractional
nanoseconds.
• Bits 19:16—period in nanoseconds.
• Bits 31:20—reserved. Set these bits to 0.
The default value is 8 ns for 125 MHz
clock. Configure this register before you
enable the MAC IP core for operations.
RW 0x80000
UG-01144
2014.12.15
TX Timestamp Registers 4-19
Configuration Registers for LL Ethernet 10G MAC Altera Corporation
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