Altera Low Latency Ethernet 10G MAC - Manual (Page 30)

Figure 3-6: Endian Conversion
55 (1) D5 CC CC EE 01 05 09 0D
55
(1)
55 88 EE AA 00 04 08 0C
55 (1) 55 EE CC 2E 03 07 0B 0F
FB 55 EE AA 88 00 02 06 0A 0E
CC
tx_312_5_clk
0 4
D1 D2 D3 D4 D5 D6 D7 D8
15 19 1D 21 25 29 2D F4 07
14 18 1C 20 24 28 2C 0A 07
13 17 1F 23 27 2B B3 07
12 16 1A 1E 22 26 2A 4E FD
1B
10
11
07
0 4
D9 D10 D11 D12 D13 D14 D15 D16 D17
D1: 555555D5
D2: EECC88CC
D3: AAEEEECC
D4: 88CCAAEE
D5: 002E0001
D6: 02030405
D7: 06070809
D8: 0A0B0C0D
D9: 0E0F1011
D10: 12131415
D11: 16171819
D12: 1A1B1C1D
D13: 1E1F2021
D14: 22232425
D15: 26272829
D16: 2A2B2C2D
D17: 4EB30AF4
avalon_st_tx_ready
avalon_st_tx_valid
avalon_st_tx_startofpacket
avalon_st_tx_endofpacket
avalon_st_tx_data[31:0]
avalon_st_tx_empty[1:0]
avalon_st_tx_error
tx_312_5_clk
xgmii_tx_control[3]
xgmii_tx_data[31:24]
xgmii_tx_control[2]
xgmii_tx_data[23:16]
xgmii_tx_control[1]
xgmii_tx_data[15:8]
xgmii_tx_control[0]
xgmii_tx_data[7:0]
Data value:
Unidirectional Feature
The MAC TX implements the unidirectional feature as specified by clause 66 in the IEEE802.3 specifica‐
tion. This is an optional feature supported only in 10G operations. When you enable this feature, two
output ports—
unidirectional_en
,
unidirectional_remote_fault_dis
— and two register fields—
UniDir_En
(Bit 0),
UniDirRmtFault_Dis
(Bit 1)— are accessible to control the TX XGMII interface.
3-8 Unidirectional Feature
UG-01144
2014.12.15
Altera Corporation Functional Description of LL Ethernet 10G MAC
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