Altera Low Latency Ethernet 10G MAC - Manual (Page 95)

Signal Condition Direction Width Description
xgmii_tx_
control[]
Use legacy Ethernet
10G MAC XGMII
interface disabled.
Enable 10GBASE-R
register mode
disabled.
Out 4
Control bits for each lane in
xgmii_tx_
data[]
.
• Lane 0:
xgmii_tx_control[0]
• Lane 1:
xgmii_tx_control[1]
• Lane 2:
xgmii_tx_control[2]
• Lane 3:
xgmii_tx_control[3]
Use legacy Ethernet
10G MAC XGMII
interface disabled.
Enable 10GBASE-R
register mode
enabled.
Out 8
8-lane SDR XGMII transmit control.
This signal connects directly to the
NativePHY IP core.
• Lane 0:
xgmii_tx_control[0]
• Lane 1:
xgmii_tx_control[1]
• Lane 2:
xgmii_tx_control[2]
• Lane 3:
xgmii_tx_control[3]
• Lane 4:
xgmii_tx_control[4]
• Lane 5:
xgmii_tx_control[5]
• Lane 6:
xgmii_tx_control[6]
• Lane 7:
xgmii_tx_control[7]
xgmii_tx_valid
Use legacy Ethernet
10G MAC XGMII
interface disabled.
Enable 10GBASE-R
register mode
enabled.
Out 1 When asserted, indicates that the data
and control buses are valid.
UG-01144
2014.12.15
XGMII TX Signals 5-13
Interface Signals for LL Ethernet 10G MAC Altera Corporation
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