Altera Low Latency Ethernet 10G MAC - Manual (Page 73)

Step Description 10G 10M, 100M or 1G
2 Convert the digital
latency in UI to ns.
123 UI * 0.097 = 11.931 ns 53 UI * 0.8 = 42.4 ns
3 Add the analog latency
to the digital latency in
ns.
11.931 ns + (-1.1 ns) = 10.831 ns 42.4 ns + (-1.1 ns) = 41.3 ns
4 Add any external PHY
delay to the total
obtained in step 3. In
this example, an
external PHY delay of
1 ns is assumed.
10.831 ns + 1 ns = 11.831 ns 41.3 ns + 1 ns = 42.3 ns
5 Convert the total
latency to ns and fns
in hexadecimal.
ns: 0xB
fns: 0.831 * 65536 = 0xD4BC ns: 0x17
fns: 0.3 * 65536 = 0x4CCC
6 Configure the
respective registers.
tx_ns_adjustment_10G
= 0xB
tx_fns_adjustment_10G
= 0xD4BC
tx_ns_adjustment_mult_speed
=
0x17
tx_fns_adjustment_mult_speed
= 0x4CCC
The Quartus II simulation model is cycle accurate for the PCS, but not for the PMA. The latency values
reported are therefore different from the hardware.
Table 4-13: PMA Delay from Simulation Model
Delay Device
PMA Mode
(bit)
Timing Adjustment
MAC Configurations
TX Register RX Register
Digita
l
Arria V GZ and
Stratix V
40 41 UI 150.5 UI 10GbE or 10G of 10M-10GbE
32 33 UI 196 UI 10GbE
10 11 UI 33.5 UI 1G/100M/10M of 10M-10GbE
Arria 10
40 151.5 UI 65.5 UI 10GbE or 10G of 10M-10GbE
10 32 UI 23.5 UI 1G/100M/10M of 10M-10GbE
RX Timestamp Registers
The RX timestamp registers are used when you turn on Enable time stamping. They are reserved when
not used.
UG-01144
2014.12.15
RX Timestamp Registers 4-21
Configuration Registers for LL Ethernet 10G MAC Altera Corporation
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