Altera Low Latency Ethernet 10G MAC - Manual (Page 45)

Figure 3-19: PHY Configuration with 10GBASE-R Register Mode Enabled.
Figure shows a block diagram of the PHY configuration when operating in 10GBASE-R mode.
Transmitter 10G PCS
Receiver 10G PCS
Transmitter PMA
Receiver PMA
Parallel Clock (Recovered)
Parallel Clock (322+ MHz)
FPGA
Fabric
Regist
er
Regist
er
Frame G
ener
at
or
CRC32
Gener
at
or
CRC32 Check
er
64B/66B E
nc
oder
and T
X SM
64B/66B D
ec
oder
and R
X SM
Scr
ambler
De
-S
crambler
Disparit
y C
heck
er
Block S
ynchr
oniz
er
Frame S
ynchr
oniz
er
Disparit
y
Gener
at
or
TX G
ear B
ox
RX G
ear B
ox
Serializ
er
Deserializ
er
CDR
rx_serial_data
tx_serial_data
Parallel Clock
Serial Clock
Parallel and Serial Clock
BER
Monitor
Div 32
Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Serial Clock
(From the ×1 Clock Lines)
Central/ Local Clock Divider
Parallel and Serial Clocks
(Only from the Central Clock Divider)
CMU PLL
64-Bit Data
8-Bit Control
64-Bit Data
8-Bit Control
66
66 32
32 66
Input Reference
Clock
64-Bit
Data
8-Bit
Control
fPLL
64-Bit
Data
8-Bit
Control
Related Information
Arria 10 Transceiver PHY User Guide
More information on how to configure the transceivers to implement 10GBASE-R functionality by using
the preset of the Arria 10 Transceivers Native PHY IP core.
XGMII Error Handling (Link Fault)
The LL Ethernet 10G MAC supports link fault generation and detection.
When the MAC RX receives a local fault, the MAC TX starts sending remote fault status (0x9c000002) on
the XGMII. If the packet transmission was in progress at the time, the remote fault bytes will override the
packet bytes until the fault condition ceases.
When the MAC RX receives a remote fault, the MAC TX starts sending IDLE bytes (0x07070707) on its
XGMII. If packet transmission was in progress at the time, the IDLE bytes will override the packet bytes
until the fault condition ceases.
The MAC considers the link fault condition has ceased if the client and the remote partner both receive
valid data in more than 127 columns.
UG-01144
2014.12.15
XGMII Error Handling (Link Fault) 3-23
Functional Description of LL Ethernet 10G MAC Altera Corporation
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