Altera Low Latency Ethernet 10G MAC - Manual (Page 47)

IEEE 1588v2
The IEEE 1588v2 option provides time stamp for receive and transmit frames in the LL Ethernet 10G
MAC IP core designs. The feature consists of Precision Time Protocol (PTP). PTP is a protocol that
accurately synchronizes all real time-of-day clocks in a network to a master clock.
The IEEE 1588v2 option has the following features:
• Supports 4 types of PTP clock on the transmit datapath:
• Master and slave ordinary clock
• Master and slave boundary clock
• End-to-end (E2E) transparent clock
• Peer-to-peer (P2P) transparent clock
• Supports PTP with the following message types:
• PTP event messages—Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp.
• PTP general messages—Follow_Up, Delay_Resp, Pdelay_Resp_Follow_Up, Announce,
Management, and Signaling.
• Supports simultaneous 1-step and 2-step clock synchronizations on the transmit datapath.
• 1-step clock synchronization—The MAC function inserts accurate timestamp in Sync PTP message
or updates the correction field with residence time.
• 2-step clock synchronization—The MAC function provides accurate timestamp and the related
fingerprint for all PTP message.
• Supports the following PHY operating speed random error:
• 10 Gbps—Timestamp accuracy of ± 1 ns
• 1 Gbps—Timestamp accuracy of ± 2 ns
• 100 Mbps—Timestamp accuracy of ± 5 ns
• Supports static error of ± 3 ns across all speeds.
• Supports IEEE 802.3, UDP/IPv4, and UDP/IPv6 protocol encapsulations for the PTP packets.
• Supports untagged, VLAN tagged, and Stacked VLAN Tagged PTP packets, and any number of MPLS
labels. The packet classifier under user control parses the packet (Ethernet packet or MPLS packet) and
gives the IP core the required offset, at which either the ToD or CF update can happen.
• Supports configurable register for timestamp correction on both transmit and receive datapaths.
• Supports ToD clock that provides streams of 64-bit and 96-bit timestamps. The 64-bit timestamp is for
transparent clock devices and the 96-bit timestamp is for ordinary clock and boundary clock devices.
Architecture
The following figure shows the overview of the IEEE 1588v2 feature.
UG-01144
2014.12.15
IEEE 1588v2 3-25
Functional Description of LL Ethernet 10G MAC Altera Corporation
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