Altera LVDS SERDES Transmitter / Receiver - Manual (Page 21)

Option Description
Use 'rx_dpll_enable' input port
Enables the path through the DPA circuitry. The option
supports dynamic, channel-by-channel control of the DPA
circuitry.
To enable the DPA circuitry for a channel, set the port for the
target channel to
1
. If this port is not used, the Quartus II
software enables all of the channels.
Use 'rx_dpll_hold' input port Prevents the DPA circuitry from switching to a new clock
phase on the target channel. Each DPA block monitors the
phase of the incoming data stream continuously and selects a
new clock phase when needed. When this port is held high, the
selected channels hold their current phase setting.
Use 'rx_fifo_reset' input port
Resets the FIFO buffer between the DPA circuit and the data
alignment circuit. The FIFO buffer holds the data passing
between the DPA and the LVDS clock domains. When this port
is held high, the FIFOs in the selected channels are reset.
This option is available only if you turn off the Use 'rx_
divfwdclk' output port and bypass the DPA FIFO option.
DPA Settings 2 (page 6)
The options on this page are available when you turn on the DPA mode.
Use 'rx_reset' input port
Resets all components of the DPA circuit. You must retrain the
DPA circuit after this port resets the DPA circuitry.
Automatically reset the bit serial FIFO
when 'rx_dpa_locked' rises for the first
time
Specifies when the bit-serial FIFO resets for DPA circuit. This
option is only available in Stratix II, Arria GX, and HardCopy
II devices.
User explicitly resets the bit serial
FIFO through 'rx_reset'
When you turn on the
rx_reset
port, the ALTLVDS_RX
parameter editor allows you to choose whether or not to
automatically reset the bit-serial FIFO when
rx_dpa_locked
signal rises for the first time. This is a useful feature because it
keeps the synchronizer FIFO in reset until the DPA locks. This
option is only available in Stratix II, Arria GX, and HardCopy
II devices.
UG-MF9504
2014.12.15
ALTLVDS_RX Parameter Settings 21
LVDS SERDES Transmitter/Receiver IP Cores User Guide Altera Corporation
Send Feedback