Altera LVDS SERDES Transmitter / Receiver - Manual (Page 46)

Related Information
• Introduction to Altera IP Cores
• PLL Clock Signals for LVDS Interface in External PLL Mode on page 62
Prototypes and Component Declarations
This section describes the prototypes and component declarations of the ALTLVDS_TX and
ALTLVDS_RX IP cores.
Verilog HDL Prototype
You can locate the Verilog HDL prototype in the Verilog Design File (.v) altera_mf.v in the <Quartus II
installation directory>\eda\synthesis directory.
VHDL Component Declaration
You can locate VHDL component declaration in the VHDL Design File (.vhd)
altera_mf_components.vhd in the <Quartus II installation directory>\libraries\vhdl\altera_mf
directory.
VHDL LIBRARY-USE Declaration
The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component Declaration.
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
Functional Description
This section describes the various receiver modes and features, the functionality of the ports and the
timing analysis of the IP cores.
Receiver Modes
The physical medium connecting the transmitter and receiver LVDS channels may introduce a skew
between the serial data and the source-synchronous clock. The instantaneous skew between each LVDS
channel and the clock also varies with the jitter on the data and clock signals as seen by the receiver.
The three receiver modes provide different options to overcome skew between the source-synchronous
clock (non-DPA, DPA) /reference clock (soft-CDR) and the serial data.
The ALTLVDS_RX IP core supports the following receiver modes:
•
DPA Mode
• Non-DPA Mode
• Soft-CDR Mode
46 Prototypes and Component Declarations
UG-MF9504
2014.12.15
Altera Corporation LVDS SERDES Transmitter/Receiver IP Cores User Guide
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