Altera LVDS SERDES Transmitter / Receiver - Manual (Page 59)

a. Right-click on the synchronous input port and select Set Input Delay.
b. The Set Input Delay dialog box appears.
c. Select the desired clock using the pull down menu. The clock name must reference the source
synchronous clock that feeds the LVDS receiver.
d. Set the appropriate values for Input Delay and Delay. Refer to Table 12 for timing constraints
options and descriptions.
e. Click Run to incorporate these values in the TimeQuest Timing Analyzer.
If no input delay is set in the TimeQuest Timing Analyzer, the receiver channel-to-channel skew (RCCS)
defaults to zero.
Setting False Path for the Asynchronous Input and Output Ports
All asynchronous input and output ports are excluded from the timing analysis of the LVDS core because
the signals on these ports are not synchronous to a IP core clock source. The internal structure of the
LVDS IP core handles the metastability of these asynchronous signals. Therefore these asynchronous
signals are set to false path.
To exclude asynchronous input and output ports from the timing analysis, perform the following steps:
1. Run full compilation for the LVDS design. Ensure that the timing analysis tool is set to TimeQuest
Timing Analyzer.
2. After full compilation completes, on the Tools menu, select TimeQuest Timing Analyzer to launch
the TimeQuest analyzer window.
3. In the Tasks list, under Diagnostic, double-click Report Unconstrained Paths to view the list of
unconstrained paths and ports of the LVDS design.
4. In the Report list, under Unconstrained Paths category, expand the Setup Analysis folder.
5. Click Unconstrained Input Port Paths to view the unconstrained input ports or click Unconstrained
Output Port Paths to view the unconstrained output ports.
6. Right-click on an ansynchronous input or output port, and select Set False Path.
After you specify all timing constraint settings for the clock signal, on the Constraints menu, click Write
SDC File to write all the constraints to a specific .sdc. Then, run full compilation for the LVDS design
again.
Setting Timing Constraints Manually in the Synopsys Design Constraint File
You can also set timing constraints manually using SDC commands in an .sdc, and include the .sdc into
your Quartus II design file.
The following example shows a simple source-synchronous interface coding, where the data is aligned
with respect to the falling edge of the clock.
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name virtual_clock_lvds -period 25
create_clock -name {rx_inclock} -period 25.000 -waveform { 0.000 12.500
} [get_ports {rx_inclock}] -add
#**************************************************************
# Create Generated Clock
#**************************************************************
derive_pll_clocks
**************************************************************
# Set Input Delay
#**************************************************************
UG-MF9504
2014.12.15
Setting False Path for the Asynchronous Input and Output Ports 59
LVDS SERDES Transmitter/Receiver IP Cores User Guide Altera Corporation
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