Altera LVDS SERDES Transmitter / Receiver - Manual (Page 47)

DPA Mode
In DPA mode, the DPA circuitry automatically chooses the best phase to compensate for the skew
between the source-synchronous clock and the received serial data.
Non-DPA Mode
Non-DPA mode allows you to statically select the optimal phase between the source synchronous clock
and the received serial data to compensate for the skew.
Soft-CDR Mode
The soft-CDR mode removes the clock from the clock-embedded data, a capability required for the serial
gigabit media independent interface (SGMII) protocol. The PLL requires a reference clock, but the
reference clock need not be source-synchronous with the data.
Clock Forwarding
In soft-CDR mode, the ALTLVDS_RX IP core divides the DPA clock and the data by the deserialization
factor. The newly divided clock signal,
rx_divfwdclk
,is then placed on the PCLK network, which carries
the clock signal to the core. In supported devices, each LVDS channel can be in soft-CDR mode and can
drive the core using the PCLK network. The clock forwarding feature is supported in Arria II GX,
Arria II GZ, Arria V, Arria V GZ, HardCopy III, HardCopy IV, Stratix III, Stratix IV, and Stratix V
devices.
Note: For more information about periphery clock networks for specific devices, refer to the Clock
Networks and PLLs chapter in volume 1 of the respective device handbook.
When using soft-CDR mode, the
rx_reset
port must not be asserted after the DPA training is asserted
because the DPA continuously chooses new phase taps from the PLL to track parts per million (ppm)
differences between the reference clock and incoming data. The parallel clock
rx_outclock
, generated by
the left and right PLL, is also forwarded to the FPGA fabric.
Note:
• For ppm tolerance specifications between the source clock and received data, refer to the appropriate
device data sheet or device handbook for each device.
• For more information about receiver modes, refer to the High-Speed Differential I/O Interfaces chapter
in the respective device handbook.
The Standard Mode on page 47 and No Output Register Mode on page 48 sections describe the
implementation of soft -CDR mode in the ALTLVDS_RX block.
Standard Mode
The following figure shows the implementation of soft-CDR mode in standard mode. In standard mode,
the first two stages of core-capture registers are created automatically by the ALTLVDS_RX parameter
editor. You must clock any additional user registers from the positive edge of the
rx_divfwdclk
clock;
using the negative edge makes it harder to meet timing, and the duty cycle is not guaranteed.
UG-MF9504
2014.12.15
DPA Mode 47
LVDS SERDES Transmitter/Receiver IP Cores User Guide Altera Corporation
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