IBM RS/6000 - Manual (Page 40)

Up to 66 MHz bus clock
Superscalar design with integrated integer, floating-point and branch units
16 KB four-way set-associative instruction cache
16 KB four-way set-associative data cache
64-bit memory interface with 32-bit addressing
Virtual memory support for up to four petabytes (2 52 )
Real memory support for up to four gigabytes
Support for Big-Endian and Little-Endian modes
Nap power management mode
Figure 6. PowerPC 604 Microprocessor Logical Block Diagram
2.2.2 The L2 Cache
The L2 cache subsystem is directly attached to the processor bus which runs at 66
MHz. It is managed by a Write-Through Look-Aside controller which interfaces to
two Cache Tag RAM modules and eight synchronous Strip Cylindrical Random
Access Memory (SCRAM) modules to form a 512 KB L2 cache assembly.
16 Introduction to PCI-Based RS/6000 Servers