Verilink PRISM 3111 (34-00242) Product Manual - Manual (Page 26)

18 C HAPTER 2: I NSTALLATION
Timing Source
Switch S2-5 and S2 -6 determine the unit clocking source. The most common
timing source for CSU /DSU applications is the network. The 3111/3112 may also
be optioned to time from an internal standard or from the high speed data interface
as shown in Table 2-11.
Test Button Loop Code
Switch S2-7 selects either an inband line loopback code (Dn) or an inband V.54
loop code (Up) for use with the front panel test button. If selected to Up, the front
panel test button performs a test on Data Port 1 only.
Test Button Mode
Switch S2-8 selects the test to be run when the Test button is pressed. Options are
BERT (Dn) or Clear (Up). Clear does not generate a pattern, it only disables alarm
monitoring and reporting.
Switch S3 Switch S3 (Figure 2-6) sets the Port 1 and Port 2 bit rates as shown in
Table 2-12 The bit rates are determined by the rate multiplier (Nx56 or Nx64) as
configured through S1-7 (Port 1) and S1-8 (Port 2) on page 15. Positions S3-6
through S3 -10 are not applicable on the 3111
Any channel not mapped to a port is allocated to the T1 DTE if that option card is
installed.
Figure 2-6 Switch S3
Table 2-11 Timing Source
S2-5 S2-6 Timing Source
Dn Dn Network
Up Dn Internal
Dn Up Port 1 EXC
Up Up T1 DTE
✍
8 7 6 5 4 3 1
Dn
Up
10 2 9
Port 1 Bit Rate Port 2 Bit Rate