Teledyne LeCroy Sierra M6-2 SAS_SATA Protocol Analyzer User Manual User Manual
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Sierra M6‐2 SAS/SATA Protocol Analyzer User Manual
453
Sierra Trainer Generation Commands
Teledyne LeCroy
Phy Capabilities Settings
OOB_SpeedNeg_Phy_start
The START bit shall be set to one. The phy’s receiver
shall use this bit to establish the timing for the
subsequent bits.
OOB_SpeedNeg_
Phy_txSSCtype
A TX SSC TYPE bit set to one indicates that the phy’s
transmitter uses center‐spreading SSC when SSC is
enabled.
A TX SSC TYPE bit set to zero indicates that the phy’s
transmitter uses down‐spreading SSC when SSC is
enabled or that the phy does not support SSC.
OOB_SpeedNeg_Phy_RLLR
The REQUESTED LOGICAL LINK RATE field indicates if
the phy supports multiplexing and, if so, the logical
link rate that the phy is requesting.
OOB_SpeedNeg_
Phy_g1WithoutSSC
A G1 WITHOUT SSC bit set to one indicates that the
phy supports G1 (i.e., 1.5 Gbps) without SSC.
A G1 WITHOUT SSC bit set to zero indicates that the
phy does not support G1 without SSC.
OOB_SpeedNeg_
Phy_g1WithSSC
A G1 WITH SSC bit set to one indicates that the phy
supports G1 (i.e., 1.5 Gbps) with SSC.
A G1 WITH SSC bit set to zero indicates that the phy
does not support G1 with SSC.
OOB_SpeedNeg_
Phy_g2WithoutSSC
A G2 WITHOUT SSC bit set to one indicates that the
phy supports G2 (i.e., 3 Gbps) without SSC.
A G2 WITHOUT SSC bit set to zero indicates that the
phy does not support G2 without SSC.
OOB_SpeedNeg_
Phy_g2WithSSC
A G2 WITH SSC bit set to one indicates that the phy
supports G2 (i.e., 3 Gbps) with SSC.
A G2 WITH SSC bit set to zero indicates that the phy
does not support G2 with SSC.
OOB_SpeedNeg_
Phy_g3WithoutSSC
A G3 WITHOUT SSC bit set to one indicates that the
phy supports G3 (i.e., 6 Gbps) without SSC.
A G3 WITHOUT SSC bit set to zero indicates that the
phy does not support G3 without SSC.
OOB_SpeedNeg_
Phy_g3WithSSC
A G3 WITH SSC bit set to one indicates that the phy
supports G3 (i.e., 6 Gbps) with SSC.
A G3 WITH SSC bit set to zero indicates that the phy
does not support G3 with SSC.
OOB_SpeedNeg_Phy_Parity
The PARITY bit provides for error detection of all the
SNW‐3 phy capabilities bits.
The PARITY bit shall be set to one or zero such that
the total number of SNW‐3 phy capabilities bits that
are set to one is even, including the START bit and the
PARITY bit.
Setting
Default
Value
Description